NXP Semiconductors PXN2020 - 29.3.4.10 Interrupt Flags 1 Register (CANx_IFLAG1)

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-25
29.3.4.10 Interrupt Flags 1 Register (CANx_IFLAG1)
This register defines the flags for 32 message buffer interrupts and FIFO interrupts. It contains one
interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding
CANx_IFLAG1 bit. If the corresponding CANx_IMASK1 bit is set, an interrupt is generated. The
interrupt flag must be cleared by writing it to ‘1’. Writing ‘0’ has no effect.
When the AEN bit in the CANx_MCR register is set (Abort enabled), while the CANx_IFLAG1 bit is set
for a MB configured as Tx, the writing access done by CPU into the corresponding MB is blocked.
When the FEN bit in the CANx_MCR register is set (FIFO enabled), the function of the eight least
significant interrupt flags (BUF7I – BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and
BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used.
Offset: Base + 0x002C Access: User read/write
0123456789101112131415
R
BUF
63I
BUF
62I
BUF
61I
BUF
60I
BUF
59I
BUF
58I
BUF
57I
BUF
56I
BUF
55I
BUF
54I
BUF
53I
BUF
52I
BUF
51I
BUF
50I
BUF
49I
BUF
48I
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
47I
BUF
46I
BUF
45I
BUF
44I
BUF
43I
BUF
42I
BUF
41I
BUF
40I
BUF
39I
BUF
38I
BUF
37I
BUF
36I
BUF
35I
BUF
34I
BUF
33I
BUF
32I
W
Reset0000000000000000
Figure 29-13. Interrupt Flag 2 Register (CANx_IFLAG2)
Table 29-14. CANx_IFLAG2 Field Descriptions
Field Description
BUFnI Message Buffer n Interrupt. Each bit represents the respective FlexCAN message buffer (MB63–MB32) interrupt.
Write 1 to clear.
0 No such occurrence.
1 The corresponding buffer has successfully completed transmission or reception.
Offset: Base + 0x0030 Access: User read/write
0123456789101112131415
R
BUF
31I
BUF
30I
BUF
29I
BUF
28I
BUF
27I
BUF
26I
BUF
25I
BUF
24I
BUF
23I
BUF
22I
BUF
21I
BUF
20I
BUF
19I
BUF
18I
BUF
17I
BUF
16I
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
15I
BUF
14I
BUF
13I
BUF
12I
BUF
11I
BUF
10I
BUF
9I
BUF
8I
BUF
7I
BUF
6I
BUF
5I
BUF
4I
BUF
3I
BUF
2I
BUF
1I
BUF
0I
W
Reset0000000000000000
Figure 29-14. Interrupt Flag 1 Register (CANx_IFLAG1)