Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-4 Freescale Semiconductor
12.1.3.3 User Test Mode (UTest)
User test mode (UTest) provides a limited set of tests to end users.
12.2 External Signal Description
V
DD
is the only externally visible power supply that is necessary for programming and erasing the flash
array. The other flash supplies are tied to the appropriate supply pads in the package. Refer to
Section 3.4.15, Power / Ground Signals, and the PXN20 Microcontroller Data Sheet.
12.3 Memory Map and Registers
This section provides a detailed description of all flash memory registers.
12.3.1 Module Memory Map
The flash memory map is shown in Table 12-1. The addresses are given as an offset to the flash memory
base address.
The flash register memory map is shown in Table 12-2. There are no program-visible registers that
physically reside inside the flash. The flash receives control and configuration information from the flash
array controller to determine operating configurations. These are part of the flash array controller’s
configuration registers mapped into the IPS address space but are described herein. These registers should
only be referenced with 32-bit accesses.
Table 12-1. Flash Memory Map
Offset from FLASH_BASE
(0x0000_0000)
Use Block
1
Partition
0x0000_0000 Low-address space L0 1
0x0000_4000 L1
0x0000_8000 L2
0x0000_C000 L3
0x0001_0000 L4 2
0x0001_4000 L5
0x0001_8000 L6
0x0001_C000 L7
0x0002_0000 L8 3
0x0003_0000 L9
0x0004_0000 Mid-address space M0 4
0x0006_0000 M1
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