Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-46 Freescale Semiconductor
31.4.6.4 LIN RX Frame Generation
The eSCI module supports two modes of LIN RX Frame generation and reception, the CPU controlled
mode and the DMA controlled mode. In the CPU controlled mode, the application provides the required
data by subsequent CPU write accesses to the eSCI LIN Transmit Register (eSCI_LTR) and retrieves the
received data by subsequent CPU read accesses to the eSCI LIN Receive Register (eSCI_LRR). In the
DMA controlled mode, the DMA controller provides the required frame configuration data in response to
DMA requests generated by the eSCI module and transfers the received frame data to the memory in
response to DMA requests generated by the eSCI module.
31.4.6.4.1 Application Controlled LIN RX Frames Generation
In this mode, the application initiates the generation of an LIN RX Frame by a sequence of subsequent
CPU write accesses to the eSCI LIN Transmit Register (eSCI_LTR). When the eSCI module has processed
the data written into eSCI LIN Transmit Register (eSCI_LTR), the TXRDY interrupt flag in the eSCI
Interrupt Flag and Status Register 2 (eSCI_IFSR2) is set.
The application must clear the TXRDY interrupt flag before writing data into the eSCI LIN Transmit
Register (eSCI_LTR) because the eSCI module sets the TXRDY one clock cycle after the write access.
The first data written to the eSCI LIN Transmit Register (eSCI_LTR) provides the Identifier and Identifier
Parity fields. The second data written defines the number of data bytes requested from the LIN slave. The
third data written defines the CRC and checksum generation. The TD bit must be set to 0 to invoke the RX
frame generation. The TO field defines the upper part of the timeout value. The fourth byte written defines
the lower part of the timeout value.
After the fourth byte is written, the generation of a LIN RX frame is started. First, a break field is
transmitted, then the synch field and the protected identifier field. After the transmission of the protected
identifier, the eSCI module starts to receive the frame data transmitted by the LIN slave. When the module
has received a complete byte field, the received data are transferred into the eSCI LIN Receive Register
(eSCI_LRR) and the receive data ready flag RXRDY in the eSCI Interrupt Flag and Status Register 2
(eSCI_IFSR2) is set.
The application can retrieve the received data by subsequent read access from eSCI LIN Receive Register
(eSCI_LRR) after checking the RXRDY flag. The application must clear the RXRDY flag immediately
after reading the eSCI LIN Receive Register (eSCI_LRR).
After the reception of the configured number of data from the slave, the module starts the reception of the
configured CRC and Checksum byte fields. These data are not transferred into the eSCI LIN Receive
Register (eSCI_LRR). The CRC and Checksum checking is performed internally. Errors are reported as
described in Section 31.4.6.5, LIN Error Reporting.
After the reception of the checksum field of the LIN RX frame, the FRC interrupt flag in the eSCI Interrupt
Flag and Status Register 2 (eSCI_IFSR2) is set.
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