NXP Semiconductors PXN2020 - 18.3.2.2 MPU Error Address Register, MPU Port 0 to 3 (MPU_EARn)

Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
18-6 Freescale Semiconductor
18.3.2.2 MPU Error Address Register, MPU Port 0 to 3 (MPU_EARn)
When the MPU detects an access error on MPU port n, the 32-bit reference address is captured in this
read-only register and the corresponding bit in the MPU_CESR[MPERR] field set. Additional information
about the faulting access is captured in the corresponding MPU_EDRn register at the same time.
1
Each MPERR bit can be cleared by writing a one to the bit location.
Table 18-3. MPU_CESR Field Descriptions
Field Description
MPERR MPU Port n Error, where the MPU port number matches the bit number. Each bit in this read-only field represents a
flag maintained by the MPU for signaling the presence of a captured error contained in the MPU_EARn and
MPU_EDRn registers. The individual bit is set when the hardware detects an error and records the faulting address
and attributes. It is cleared when the corresponding bit is written to a logical one. If another error is captured at the
exact same cycle as a write of a logical one, this flag remains set. A find-first-one instruction (or equivalent) can be
used to detect the presence of a captured error.
0 The corresponding MPU_EARn/MPU_EDRn registers do not contain an unread captured error
1 The corresponding MPU_EARn/MPU_EDRn registers do contain an unread captured error
Note: Bit 0 indicates a 512 KB RAM access protection error, bit 1 represents an 80 KB RAM access protection error,
bit 2 represents an AIPS_A access protection error, and bit 3 represents an AIPS_B access protection error.
HRL Hardware Revision Level. This 4-bit read-only field specifies the MPU’s hardware and definition revision level. It can
be read by software to determine the functional definition of the module. This field reads as 0 on PXN20 .
NSP Number of MPU Ports. This 4-bit read-only field specifies the number of MPU ports [1–8] connected to the MPU.
This field reads as 0b0011 on PXN20.
NRGD Number of Region Descriptors. This 4-bit read-only field specifies the number of region descriptors implemented in
the MPU. The defined encodings include:
0000 8 region descriptors.
0010 16 region descriptors.
This field reads as 0b0010 on PXN20.
VLD Valid. This bit provides a global enable/disable for the MPU.
0 The MPU is disabled.
1 The MPU is enabled.
While the MPU is disabled, all accesses from all bus masters are allowed.