NXP Semiconductors PXN2020 - 26.5.2.4 Module Configuration Register (MCR)

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-14 Freescale Semiconductor
26.5.2.4 Module Configuration Register (MCR)
This register defines the global configuration of the controller.
Base + 0x0002 Write: MEN, SBFF, SCM, CHB, CHA, FUM, FAM, CLKSEL, BITRATE: Disabled Mode
SFFE: Disabled Mode or POC:config
0123456789101112131415
R
MEN SBFF SCM CHB CHA SFFE
0
0FUMFAM
0
CLK
SEL
BITRATE
0
W
Reset0000000000000000
Figure 26-3. Module Configuration Register (MCR)
Table 26-8. MCR Field Descriptions
Field Description
MEN Module Enable — This bit indicates whether or not the controller is in the Disabled Mode. The application
requests the controller to leave the Disabled Mode by writing 1 to this bit Before leaving the Disabled Mode, the
application must configure the SCM, SBFF, CHB, CHA, TMODE, BITRATE values. For details see
Section 26.1.6, Modes of Operation.
0 Write: ignored, controller disable not possible.
Read: controller disabled.
1 Write: enable controller.
Read: controller enabled.
Note: If the controller is enabled it cannot be disabled.
SBFF System Bus Failure Freeze — This bit controls the behavior of the controller in case of a system bus failure.
0 Continue normal operation.
1 Transition to freeze mode.
SCM Single Channel Device Mode — This control bit defines the channel device mode of the controller as described
in Section 26.6.10, Channel Device Modes.
0 controller works in dual channel device mode.
1 controller works in single channel device mode.
CHB
CHA
Channel Enable — protocol related parameter: pChannels
The semantic of these control bits depends on the channel device mode controlled by the SCM bit and is given
Ta bl e 2 6- 9.
SFFE Synchronization Frame Filter Enable — This bit controls the filtering for received synchronization frames. For
details see Section 26.6.15, Sync Frame Filtering.
0 Synchronization frame filtering disabled.
1 Synchronization frame filtering enabled.
FUM FIFO Update Mode — This bit controls the FIFO update behavior when the interrupt flags GIFER[FAFAIF] and
DIFER[FAFBIF] are written by the application (see Section 26.6.9.8, FIFO Update).
0 FIFOA (FIFOB) is updated on writing 1 to GIFER[FAFAIF] (GIFER[FAFBIF]).
1 FIFOA (FIFOB) is not updated on writing 1 to GIFER[FAFAIF] (GIFER[FAFBIF]).
FAM FIFO Address Mode — This bit controls the location of the system memory base address for the FIFOs (see
Section 26.6.9.2, FIFO Configuration).
0 FIFO Base Address located in System Memory Base Address Register (SYMBADR).
1 FIFO Base Address located in Receive FIFO System Memory Base Address Register (RFSYMBADR).