NXP Semiconductors PXN2020 - Chapter 17 Peripheral Bridge (AIPS-lite); 17.1 Introduction; 17.1.1 Block Diagram; 17.1.2 Features

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 17-1
Chapter 17
Peripheral Bridge (AIPS-lite)
17.1 Introduction
The AIPS-lite acts as an interface between the system bus and lower bandwidth peripherals.
17.1.1 Block Diagram
A simplified block diagram of the AIPS-lite illustrates the functionality and interdependence of major
blocks (see Figure 17-1).
Figure 17-1. AIPS-lite Block Diagram
17.1.2 Features
The AIPS-lite has these major features:
• AIPS-lite supports the IPS slave interface signals. This interface is meant for slave peripherals
only.
• AIPS-lite supports 32-bit IPS peripherals. (Byte, halfword, and word reads and write are supported
to each.)
• Read and write accesses of 32 bits or less require two clocks, provided they do not cross a 32-bit
boundary.
— Read and write accesses that cross a 32-bit boundary are not supported.
• The peripherals connected to the AIPS-lite may be configured in groups to run at less than the
system clock frequency. See Section 5.3, Clock Dividers, in Chapter 5, System Clock Description,
for a description of these groups.
On-Chip Peripherals
32
AMBA AHB
AMBA AHB
AMBA AHB
MUX Logic
AXBS
32
32
32
Peripheral
Bridge
(AIPS-lite)