NXP Semiconductors PXN2020 - 11.5.2 Reset Operation

General-Purpose Static RAM (SRAM)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 11-5
11.5.2 Reset Operation
A destructive reset is associated with an event after which critical register or memory content can no longer
be guaranteed, if a write operation occurred during the event.
Destructive resets are as follows.
Table 11-1. Number of Wait States Required for SRAM Operations
Current Operation Previous Operation Number of Wait States Required
Read Operation
Read
Idle
1Pipelined read
Burst read
64-bit write 2
8-, 16-, or 32-bit write
0
(read from the same address)
1
(read from a different address)
Pipelined read Read 0
Burst read
Idle
1,0,0,0Pipelined read
Burst read
64-bit write 2,0,0,0
8-, 16-, or 32-bit write
0,0,0,0
(read from the same address)
1,0,0,0
(read from a different address)
Write Operation
8-, 16-, or 32-bit write
Idle
1
Read
Pipelined 8-, 16-, or 32-bit write
2
64-bit write
8-, 16-, or 32-bit write 0
(write to the same address)
Pipelined 8-, 16-, or 32-bit write 8-, 16-, or 32-bit write 0
64-bit write
Idle
064-bit write
Read
64-bit burst write
Idle
0,0,0,064-bit write
Read