NXP Semiconductors PXN2020 - 27.3.2.8 Control Base Address Configuration Register (CBCR)

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 27-15
27.3.2.8 Control Base Address Configuration Register (CBCR)
The Control Base Address Configuration Register (CBCR) allows system software to define the base
address for control RX/TX system memory buffers.
Offset: MLB_BASE + 0x0024 Access: User read/write
0123456789101112131415
R
ARBA[31:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ATBA[31:16]
W
Reset0000000000000000
Figure 27-8. Asynchronous Base Address Configuration Register (ABCR)
Table 27-14. ABCR Field Descriptions
Field Description
ARBA
[31:16]
Asynchronous Receive Base Address. This base address is shared by all asynchronous RX channels and defines
the upper 16 bits of the 32-bit system memory address for these channels.
ATB A
[31:16]
Asynchronous Transmit Base Address. This base address is shared by all asynchronous TX channels and defines
the upper 16 bits of the 32-bit system memory address for these channels.
Offset: MLB_BASE + 0x0028 Access: User read/write
0123456789101112131415
R
CRBA[31:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CTBA[31:16]
W
Reset0000000000000000
Figure 27-9. Control Base Address Configuration Register (CBCR)