NXP Semiconductors PXN2020 - 30.3.2.7 DSPI POP RX FIFO Register (DSPI_POPR); 30.3.2.8 DSPI Transmit FIFO Registers 0-15 (DSPI_TXFRn)

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-21
30.3.2.7 DSPI POP RX FIFO Register (DSPI_POPR)
The DSPI_POPR provides a means to read the RX FIFO. See Section 30.4.3.5, Receive First-In First-Out
(RX FIFO) Buffering Mechanism, for a description of the RX FIFO operations. 8- or 16-bit read accesses
to the DSPI_POPR read from the RX FIFO and update the counter and pointer.
30.3.2.8 DSPI Transmit FIFO Registers 0–15 (DSPI_TXFRn)
The DSPI_TXFRn registers provide visibility into the TX FIFO for debugging purposes. Each register is
an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the DSPI_TXFRn
registers does not alter the state of the TX FIFO.
PCSn Peripheral Chip Select 0–7. The PCS bits select which PCS signals are asserted for the transfer.
0 Negate the PCS[x] signal.
1 Assert the PCS[x] signal.
TXDATA Transmit Data. The TXDATA field holds SPI data to be transferred according to the associated SPI command.
Offset: DSPI_BASE + 0x0038 Access: Read
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RRXDATA
W
Reset0000000000000000
Figure 30-9. DSPI POP RX FIFO Register (DSPI_POPR)
Table 30-15. DSPI_POPR Field Descriptions
Field Description
RXDATA Received Data. The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the Pop Next Data
Pointer.
Table 30-14. DSPI_PUSHR Field Descriptions (continued)
Field Description