NXP Semiconductors PXN2020 - 27.3.2.9 Isochronous Base Address Configuration Register (IBCR); 27.3.2.10 Channel Interrupt Configuration Register (CICR)

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
27-16 Freescale Semiconductor
27.3.2.9 Isochronous Base Address Configuration Register (IBCR)
The Isochronous Base Address Configuration Register (IBCR) allows system software to define the base
address for isochronous RX/TX system memory buffers.
27.3.2.10 Channel Interrupt Configuration Register (CICR)
The Channel Interrupt Configuration Register (CICR) reflects the channel interrupt status of the individual
MLB logical channels. These bits are set by hardware when a channel interrupt is generated. The channel
interrupt bits are sticky and can only be reset by software.
Table 27-15. CBCR Field Descriptions
Field Description
CRBA
[31:16]
Control Receive Base Address. This base address is shared by all control RX channels and defines the upper 16
bits of the 32-bit system memory address for these channels.
CTBA
[31:16]
Control Transmit Base Address. This base address is shared by all control TX channels and defines the upper 16
bits of the 32-bit system memory address for these channels.
Offset: MLB_BASE + 0x002C Access: User read/write
0123456789101112131415
R
IRBA[31:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ITBA[31:16]
W
Reset0000000000000000
Figure 27-10. Isochronous Base Address Configuration Register (IBCR)
Table 27-16. IBCR Field Descriptions
Field Description
IRBA
[31:16]
Isochronous Receive Base Address. This base address is shared by all Isochronous RX channels and defines the
upper 16 bits of the 32-bit system memory address for these channels.
ITBA
[31:16]
Isochronous Transmit Base Address. This base address is shared by all Isochronous TX channels and defines the
upper 16 bits of the 32-bit system memory address for these channels.