NXP Semiconductors PXN2020 - 8.3.2.50 Masked Serial GPO Register for DSPI_C High (SIU_DSPICH); 8.3.2.51 Masked Serial GPO Register for DSPI_C Low (SIU_DSPICL)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-60 Freescale Semiconductor
8.3.2.50 Masked Serial GPO Register for DSPI_C High (SIU_DSPICH)
The SIU_DSPICH register allows any combination of bits in the top half of the 32-bit serialized data frame
from DSPI_C to be updated with a single 32-bit write operation, while allowing other bits to maintain their
previous state. This is accomplished by writing a 16-bit masked value coherently with an update value
contained in a 16-bit output field, and only updating those bits in the output register for which the
corresponding mask bit is set.
8.3.2.51 Masked Serial GPO Register for DSPI_C Low (SIU_DSPICL)
The SIU_DSPICL register allows any combination of bits in the bottom half of the 32-bit serialized data
frame from DSPI_C to be updated with a single 32-bit write operation, while allowing other bits to
Table 8-36. SIU_DSPIBL Field Descriptions
Field Description
MASKn Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_B.
0 The previous value defined by GPO for DSPI_B is maintained.
1 The corresponding GPO for DSPI_B is written with the value defined by the DATAn field.
DATAn Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_B output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_B when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_B when this output is selected in the DSPI
serialization module.
Offset: SIU_BASE + 0x0D10 Access: User read/write
0123456789101112131415
R
MASK
31
MASK
30
MASK
29
MASK
28
MASK
27
MASK
26
MASK
25
MASK
24
MASK
23
MASK
22
MASK
21
MASK
20
MASK
19
MASK
18
MASK
17
MASK
16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DATA
31
DATA
30
DATA
29
DATA
28
DATA
27
DATA
26
DATA
25
DATA
24
DATA
23
DATA
222
DATA
21
DATA
20
DATA
19
DATA
18
DATA
17
DATA
16
W
Reset0000000000000000
Figure 8-58. Masked Serial GPO Register for DSPI_C High (SIU_DSPICH)
Table 8-37. SIU_DSPICH Field Descriptions
Field Description
MASKn Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_C.
0 The previous value defined by GPO for DSPI_C is maintained.
1 The corresponding GPO for DSPI_C is written with the value defined by the DATAn field.
DATAn Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_C output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_C when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_C when this output is selected in the DSPI
serialization module.