Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-3
24.1.3.2 Debug Mode
In debug mode, the eDMA does not accept new transfer requests when its debug input signal is asserted.
If the signal is asserted during transfer of a block of data described by a minor loop in the current active
channel’s TCD, the eDMA continues operation until completion of the minor loop.
24.2 External Signal Description
The eDMA has no external signals.
24.3 Memory Map and Registers
This section provides a detailed description of all eDMA registers.
24.3.1 Module Memory Map
The eDMA memory map is shown in Table 24-1. The address of each register is given as an offset to the
eDMA base address. Registers are listed in address order, identified by complete name and mnemonic, and
list the type of accesses allowed. Table 24-2 shows a graphical representation of the same memory map.
The eDMA’s programming model is partitioned into two regions: the first region defines a number of
registers providing control functions; however, the second region corresponds to the local transfer control
descriptor memory.
Some registers are implemented as two 32-bit registers, and include H and L suffixes, signaling the high
and low portions of the control function.
Table 24-1. eDMA Memory Map
Offset from
EDMA_BASE
(0xFFF4_4000)
Register Access Reset Value Section/Page
Size
0x0000 EDMA_CR—eDMA control register R/W 0x0000_0400 24.3.2.1/24-8 32
0x0004 EDMA_ESR—eDMA error status register R 0x0000_0000 24.3.2.2/24-10 32
0x0008 Reserved
0x000C EDMA_ERQRL—eDMA enable request register
(channels 31–00)
R/W 0x0000_0000 24.3.2.3/24-12 32
0x0010 Reserved
0x0014 EDMA_EEIRL—eDMA enable error interrupt register
(channels 31–00)
R/W 0x0000_0000 24.3.2.4/24-13 32
0x0018 EDMA_SERQR—eDMA set enable request register W 0x00 24.3.2.5/24-14 8
0x0019 EDMA_CERQR—eDMA clear enable request register W 0x00 24.3.2.6/24-15 8
0x001A EDMA_SEEIR—eDMA set enable error interrupt register W 0x00 24.3.2.7/24-15 8
0x001B EDMA_CEEIR—eDMA clear enable error interrupt register W 0x00 24.3.2.8/24-16 8
0x001C EDMA_CIRQR—eDMA clear interrupt request register W 0x00 24.3.2.9/24-17 8
To Next Page
Loading...
