NXP Semiconductors PXN2020 - Page 526

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-6 Freescale Semiconductor
0x1240 TCD18—eDMA transfer control descriptor 18 R/W —
1
24.3.2.17/24-23 256
0x1260 TCD19—eDMA transfer control descriptor 19 R/W —
1
24.3.2.17/24-23 256
0x1280 TCD20—eDMA transfer control descriptor 20 R/W —
1
24.3.2.17/24-23 256
0x12A0 TCD21—eDMA transfer control descriptor 21 R/W —
1
24.3.2.17/24-23 256
0x12C0 TCD22—eDMA transfer control descriptor 22 R/W —
1
24.3.2.17/24-23 256
0x12E0 TCD23—eDMA transfer control descriptor 23 R/W —
1
24.3.2.17/24-23 256
0x1300 TCD24—eDMA transfer control descriptor 24 R/W —
1
24.3.2.17/24-23 256
0x1320 TCD25—eDMA transfer control descriptor 25 R/W —
1
24.3.2.17/24-23 256
0x1340 TCD26—eDMA transfer control descriptor 26 R/W —
1
24.3.2.17/24-23 256
0x1360 TCD27—eDMA transfer control descriptor 27 R/W —
1
24.3.2.17/24-23 256
0x1380 TCD28—eDMA transfer control descriptor 28 R/W —
1
24.3.2.17/24-23 256
0x13A0 TCD29—eDMA transfer control descriptor 29 R/W —
1
24.3.2.17/24-23 256
0x13C0 TCD30—eDMA transfer control descriptor 30 R/W —
1
24.3.2.17/24-23 256
0x13E0 TCD31—eDMA transfer control descriptor 31 R/W —
1
24.3.2.17/24-23 256
0x1400–0x17FF Reserved
1
See specific register description.
Table 24-2. eDMA 32-bit Memory Map—Graphical View
Address Register
0xFFF4_4000 eDMA Control Register (EDMA_CR)
0xFFF4_4004 eDMA Error Status (EDMA_ESR)
0xFFF4_4008 Reserved
0xFFF4_400C eDMA Enable Request
(EDMA_ERQRL, channels 31–16)
eDMA Enable Request
(EDMA_ERQRL, channels 15–00)
0xFFF4_4010 Reserved
0xFFF4_4014 eDMA Enable Error Interrupt Low
(EDMA_EEIRL, channels 31–16)
eDMA Enable Error Interrupt Low
(EDMA_EEIRL, Channels 15–00)
0xFFF4_4018 eDMA Set Enable
Request
(EDMA_SERQR)
eDMA Clear Enable
Request
(EDMA_CERQR)
eDMA Set Enable Error
Interrupt
(EDMA_SEEIR)
eDMA Clear Enable Error
Interrupt
(EDMA_CEEIR)
0xFFF4_401C eDMA Clear Interrupt
Request
(EDMA_CIRQR)
eDMA Clear
Error
(EDMA_CER)
eDMA Set Start Bit,
Activate Channel
(EDMA_SSBR)
eDMA Clear Done
Status Bit
(EDMA_CDSBR)
0xFFF4_4020 Reserved
Table 24-1. eDMA Memory Map (continued)
Offset from
EDMA_BASE
(0xFFF4_4000)
Register Access Reset Value Section/Page Size