NXP Semiconductors PXN2020 - 19.2.2.3 ECC Status Register (ESR)

Error Correction Status Module (ECSM)
PXN20 Microcontroller Reference Manual, Rev. 1
19-6 Freescale Semiconductor
19.2.2.3 ECC Status Register (ESR)
The ECC status register is an 8-bit control register for signaling which types of properly enabled ECC
events have been detected. The ESR signals the last properly enabled memory event to be detected. An
ECC interrupt request is asserted if any flag bit is asserted and its corresponding enable bit is asserted.
The ECSM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the
association between the ESR and the corresponding address and attribute registers, which are loaded on
each occurrence of an properly enabled ECC event. If there is a pending ECC interrupt and another
properly enabled ECC event occurs, the ECSM hardware automatically handles the ESR reporting,
clearing the previous data and loading the new state and thus guaranteeing that only a single flag is
asserted.
To maintain the coherent software view of the reported event, the following sequence in the ECSM error
interrupt service routine is suggested:
1. Read the ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ESR and verify the current contents matches the original contents. If the two values
are different, repeat from step one.
4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.
See Figure 19-3 and Table 19-5 for the ECC status register definition.
Offset: ECSM_BASE_ADDR + 0x0047 Access: User read/write
01234567
R 0 0 PR1BC PF1BC 0 0 PRNCE PFNCE
W
w1c w1c w1c w1c
Reset00000000
Figure 19-3. ECC Status (ESR) Register
Table 19-5. ESR Field Descriptions
Field Description
PR1BC Platform RAM 1-bit Correction. This bit can only be set when ECR[EPR1BR] is asserted. The occurrence of a
properly-enabled single-bit RAM correction generates an ECSM ECC interrupt request. The address, attributes and
data are also captured in the PREAR, PRESR, PREMR, PREAT, and PREDR registers. To clear this interrupt flag,
write a 1 to this bit. Writing a 0 has no effect.
0 No reportable single-bit platform RAM correction has been detected.
1 A reportable single-bit platform RAM correction has been detected.
PF1BC Platform Flash 1-bit Correction. This bit can only be set when ECR[EPF1BR] is asserted. The occurrence of a
properly-enabled single-bit flash correction generates an ECSM ECC interrupt request. The address, attributes and
data are also captured in the PFEAR, PFEMR, PFEAT, and PFEDR registers. To clear this interrupt flag, write a 1
to this bit. Writing a 0 has no effect.
0 No reportable single-bit platform flash correction has been detected.
1 A reportable single-bit platform flash correction has been detected.