NXP Semiconductors PXN2020 - 24.3.2.1 eDMA Control Register (EDMA_CR)

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-8 Freescale Semiconductor
24.3.2.1 eDMA Control Register (EDMA_CR)
The 32-bit EDMA_CR defines the basic operating configuration of the eDMA.
Arbitration among the channels can be configured to use a fixed priority or a round robin. In fixed-priority
arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers. See Section 24.3.2.16, eDMA Channel n Priority Registers
(EDMA_CPRn). In round-robin arbitration mode, the channel priorities are ignored and the channels
within each group are cycled through, from channel 31 down to channel 0,without regard to priority.
Minor loop offsets are address offset values added to the final source address (SADDR) or destination
address (DADDR) upon minor loop completion. When minor loop offsets are enabled, the minor loop
offset (MLOFF) is added to the final source address (SADDR) or to the final destination address
(DADDR) or to both addresses prior to the addresses being written back into the TCD. If the major loop
is complete, the minor loop offset is ignored and the major loop address offsets (SLAST and
DLAST_SGA) are used to compute the next TCR.SADDR and TCR.DADDR values.
When minor loop mapping is enabled (EDMA_CR[EMLM] = 1), TCDn word2 is redefined. A portion of
TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to specify that the minor loop
offset should be applied to the source address (SADDR) upon minor loop completion, a destination enable
bit (DMLOE) to specify the minor loop offset should be applied to the destination address (DADDR) upon
minor loop completion, and the sign extended minor loop offset value (MLOFF). The same offset value
(MLOFF) is used for both source and destination minor loop offsets.
When either of the minor loop offsets is enabled (SMLOE is set or DMLOE is set), the NBYTES field is
reduced to 8 bits. When both minor loop offsets are disabled (SMLOE is cleared and DMLOE is cleared),
the NBYTES field becomes a 30-bit vector.
When minor loop mapping is disabled (EDMA_CR[EMLM] = 0), all 32 bits of TCDn word2 are assigned
to the NBYTES field. See Section 24.3.2.17, Transfer Control Descriptor (TCD), for more details.
Offset: EDMA_BASE + 0x0000 Access: User read/write
01234567 8 9101112131415
R00000000 0 0000 0
CXFR ECX
W
Reset00000000 0 0000 0 00
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000
GRP1
PRI
0
GRP0
PRI
EMLM CLM HALT HOE ERGA ERCA EDBG
0
W
Reset00000000 0 0000 1 00
Figure 24-2. eDMA Control Register (EDMA_CR)