e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-29
13.3.3 Interrupt Types
The interrupts implemented in the device and the exception conditions that cause them are listed in
Table 13-12.
Table 13-11. L1CFG0 Field Descriptions
Bits Name Description
0–1 CARCH
Cache architecture
01 The cache architecture is unified
2CWPA
Cache way partitioning available
1 The cache supports partitioning of way availability for I/D accesses
3CFAHA
Cache flush all by hardware available
0 The cache does not support flush all in hardware
4CFISWA
Cache flush/invalidate by set and way available
1 The cache supports flushing/invalidation by set and way via the L1FINV0 spr
5–6 — Reserved—read as zeros
7–8 CBSIZE
Cache block size
00 The cache implements a block size of 32 bytes
9–10 CREPL
Cache replacement policy
10 The cache implements a pseudo-round-robin replacement policy
11 CLA
Cache locking APU available
1 The cache implements the line locking APU
12 CPA
Cache parity available
1 The cache implements parity
13:20 CNWAY
Number of ways in the data cache
0x03 - The cache is 4-way set-associative
0x07 - The cache is 8-way set-associative
21:31 CSIZE
Cache size
0x020 - The size of the cache is 32 KB
Table 13-12. Interrupts and Conditions
Interrupt Type
Interrupt
Vector Offset
Register
Enables
1
Core Register
in Which
State
Information is
Saved
Causing Conditions
System reset none,
vector to
0xFFFF_FFFC
• Reset by assertion of RESET
• Watchdog timer reset control
• Debug reset control
Critical input IVOR0
2
CE = 1 • Non-maskable interrupt request
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