NXP Semiconductors PXN2020 - 26.5.2.52 Receive FIFO Periodic Timer Register (RFPTR)

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-57
These registers define the system memory base address for the receive FIFO if the FIFO address mode bit
MCR[FAM] is set to 1. The system memory base address is used by the BMIF to calculate the physical
memory address for system memory accesses for the FIFOs.
26.5.2.52 Receive FIFO Periodic Timer Register (RFPTR)
This register holds periodic timer duration for the periodic FIFO timer. The periodic timer applies to both
FIFOs (see Section 26.6.9.3, FIFO Periodic Timer).
Base + 0x00E8 Write: Disabled Mode
0123456789101112131415
R
SMBA[31:16]
W
Reset0000000000000000
Figure 26-51. Receive FIFO System Memory Base Address High Register (RFSYMBADHR)
Base + 0x00EA Write: Disabled Mode
0123456789101112131415
R
SMBA[15:4]
0000
W
Reset0000000000000000
Figure 26-52. Receive FIFO System Memory Base Address Low Register (RFSYMBADLR)
Table 26-60. RFSYMBADR Field Descriptions
Field Description
SMBA System Memory Base Address — This is the value of the system memory base address for the receive FIFO
if the FIFO address mode bit MCR[FAM] is set to 1. It is defines as a byte address.
Base + 0x00EC Write: POC:config
0123456789101112131415
R0 0
PTD
W
Reset0000000000000000
Figure 26-53. Receive FIFO Periodic Timer Register (RFPTR)
Table 26-61. RFPTIR Field Descriptions
Field Description
PTD Periodic Timer Duration — This value defines the periodic timer duration in terms of macroticks.
0000 Timer stays expired.
3FFF Timer never expires.
other Timer expires after specified number of macroticks, expires and is restarted at each cycle start.