NXP Semiconductors PXN2020 - 7.3.2.3 FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2)

Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 7-7
7.3.2.3 FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2)
This is the second of two enhanced versions of the FMPLL synthesizer control register used to access
enhanced features in the FMPLL. The bit fields in the ESYNCR2 behave as described in Figure 7-4.
Table 7-5. Pre-divider Ratios
EPREDIV Input Divide Ratio (EPREDIV+1)
0000 1 (default for PXN20)
0001 2
0010 3
0011 4
0100 5
0101 6
0110 Invalid
0111 8
1000 Invalid
1001 10
1010–1111 Invalid
Table 7-6. Feedback Divide Ratios
EMFD Feedback Divide Ratio (EMFD+16)
0000_0000–0001_1111 Invalid
0010_0000 48
0010_0001 49
0010_0010 50
0010_0011 51
0010_0100 52
0010_0101 53
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0011_0000
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64 (default for PXN20)
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1000_0100 148
1000_0101–1111_1111 Invalid