NXP Semiconductors PXN2020 - 3.2.1 I;O Power and Ground Segmentation

Signal Description
PXN20 Microcontroller Reference Manual, Rev. 1
3-18 Freescale Semiconductor
3.2.1 I/O Power and Ground Segmentation
Table 3-2 gives the preliminary power/ground segmentation. Each segment provides the power and ground
for the I/O pins and can be powered by any voltage within the allowed voltage range regardless of the
power on the other segments. The power/ground segmentation applies regardless of whether a particular
pin is configured for its primary function or GPIO.
Table 3-2. PXN20 Power Segmentation
Pin
Name
Function Description Voltage
1
1
Nominal voltages.
Package Pin Locations
208 256
V
DD
Internal Logic Power 1.2 V D4, D10, H4, G13, K13, N5 D4, D10, H4, G13, K13, N5
V
DDE1
External I/O Power 3.3 or 5.0 V D6 D6
V
DDE2
L4 L4
V
DDE3
J13 J13
V
DDE4
N10 N10
V
DDA
Analog Power 3.3 or 5.0 V B15 B15
V
DD33
3.3 V I/O Power 3.3 V L13 L13
V
DDEMLB
Media Local Bus Power 2.5 or 3.3 V K4 K4
V
DDENEX
2
2
Dedicated Nexus power pin on 256-pin package only. On the 208-pin package, VDDENEX is tied to VSS internal to the
package substrate and is not available externally.
Nexus Power 3.3 V — E6, K11, L7
V
RCSEL
Voltage Regulator Select V
SSA
/ V
DDA
H13 H13
V
RC
Voltage Regulator Control Voltage 3.3 or 5.0 V B10 B10
V
RCCTL
Voltage Regulator Control Output
—
3
3
Base current to external NPN power transistor. Voltage may vary.
B11 B11
V
DDSYN
Clock Synthesizer Power 3.3 V A12 A12
V
RH
Analog High Voltage Reference 5.0 V B16 B16
V
RL
Analog Low Voltage Reference 0 V C16 C16
V
SS
Ground 0 V A1, A16, D7, G4, G[7:10],
H[7:10], J[7:10], K[7:10], N13,
T1, T16
A1, A16, D7, E[7:12], F[7:12],
G4, G[6:12], H[7:12], J[7:12],
K[6:10], K12, L[8:10], L12,
N13, T1, T16
V
SSA
Analog Ground 0 V C15 C15
V
SSSYN
Clock Synthesizer Ground 0 V A15 A15