NXP Semiconductors PXN2020 - 32.3.2.6 I2 C Bus Interrupt Configuration Register (IBIC); 32.4 Functional Description; 32.4.1 I-Bus Protocol

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 32-11
32.3.2.6 I
2
C Bus Interrupt Configuration Register (IBIC)
32.4 Functional Description
32.4.1 I-Bus Protocol
The I
2
C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open-drain or open-collector outputs. A logical AND function is exercised on
both lines with external pullup resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer, and STOP signal. They are described briefly in the following sections and illustrated in
Figure 32-10.
Offset: 0x0005 Access: User read/write
01234567
R
BIIE
0000000
W
Reset00000000
Figure 32-9. I
2
C Bus Interrupt Configuration Register (IBIC)
Table 32-7. IBIC Field Descriptions
Field Description
BIIE Bus Idle Interrupt Enable Bit. This configuration bit can be used to enable the generation of an interrupt after the I
2
C
bus becomes idle. After this bit is set, an IBB high-low transition sets the IBIF bit. This feature can be used to signal
to the CPU the completion of a STOP on the I
2
C bus.
0 Bus idle interrupts disabled.
1 Bus idle interrupts enabled.
bits 1–7 Reserved for future use. A read returns 0; must be written as 0.