FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-153
26.7.1.2 Protocol Initialization
This section describes the protocol related initialization steps.
1. Configure the Protocol Engine.
a) issue CONFIG command via Protocol Operation Control Register (POCR)
b) wait for POC:config in Protocol Status Register 0 (PSR0)
c) configure the PCR0,..., PCR30 registers to set all protocol parameters
2. Configure the Message Buffers and FIFOs.
a) set the number of message buffers used and the message buffer segmentation in the Message
Buffer Segment Size and Utilization Register (MBSSUTR)
b) define the message buffer data size in the Message Buffer Data Size Register (MBDSR)
c) configure each message buffer by setting the configuration values in the Message Buffer
Configuration, Control, Status Registers (MBCCSRn), Message Buffer Cycle Counter Filter
Registers (MBCCFRn), Message Buffer Frame ID Registers (MBFIDRn), Message Buffer
Index Registers (MBIDXRn)
d) configure the FIFOs
e) issue CONFIG_COMPLETE command via Protocol Operation Control Register (POCR)
f) wait for POC:ready in Protocol Status Register 0 (PSR0)
After this sequence, the controller is configured as a FlexRay node and is ready to integrate into the
FlexRay cluster.
26.7.2 Shut Down Sequence
This section describes a secure shut down sequence to stop the controller gracefully. The main targets of
this sequence are
• finish all ongoing reception and transmission
• do not corrupt FlexRay bus and do not disturb ongoing FlexRay bus communication
For a graceful shutdown the application shall perform the following tasks:
1. Disable all enabled message buffers.
a) repeatedly write 1 to MBCCSRn[EDT] until MBCCSRn[EDS] == 0.
2. Stop Protocol Engine.
a) issue HALT command via Protocol Operation Control Register (POCR)
b) wait for POC:halt in Protocol Status Register 0 (PSR0)
26.7.3 Number of Usable Message Buffers
This section describes the relationship between the number of message buffers that can be utilized and the
required minimum CHI clock frequency. Additional constraints for the minimum CHI clock frequency are
given in Section 26.3, Controller Host Interface Clocking.
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