NXP Semiconductors PXN2020 - 22.3.2 Register Descriptions; 22.3.2.1 PIT Module Control Register (PITMCR)

Periodic Interrupt Timer (PIT)
PXN20 Microcontroller Reference Manual, Rev. 1
22-4 Freescale Semiconductor
22.3.2 Register Descriptions
This section lists the PIT registers and describes the registers and their bit fields.
22.3.2.1 PIT Module Control Register (PITMCR)
This register controls whether the timer clocks should be enabled and whether the timers should run in
debug mode.
Timer Channel 7
0x0160 LDVAL7—Timer 7 Load Value Register R/W 0x0000_0000 22.3.2.2/22-5
0x0164 CVAL7—Timer 7 Current Value Register R/W 0x0000_0000 22.3.2.3/22-5
0x0168 TCTRL7—Timer 7 Control Register R/W
1
0x0000_0000 22.3.2.4/22-6
0x016C TFLG7—Timer 7 Flag Register R/W
1
0x0000_0000 22.3.2.5/22-7
Timer Channel 8
0x0170 LDVAL8—Timer 8 Load Value Register R/W 0x0000_0000 22.3.2.2/22-5
0x0174 CVAL8—Timer 8 Current Value Register R/W 0x0000_0000 22.3.2.3/22-5
0x0178 TCTRL8—Timer 8 Control Register R/W
1
0x0000_0000 22.3.2.4/22-6
0x017C TFLG8—Timer 8 Flag Register R/W
1
0x0000_0000 22.3.2.5/22-7
0x0180–0x03FF Reserved
1
Some bits are read-only.
Offset: PIT_BASE + 0x0000 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000000000
MDIS FRZ
W
Reset0000000000000010
Figure 22-2. PIT Module Control Register (PITMCR)
Table 22-2. PIT Memory Map (continued)
Offset from
PIT_BASE
(0xFFFE_0000)
Register Access Reset Value Section/Page