NXP Semiconductors PXN2020 - 28.3.2.5 eMIOS200 A Register (EMIOS_CADR[n]); 28.3.2.6 eMIOS200 B Register (EMIOS_CBDR[n])

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-12 Freescale Semiconductor
28.3.2.5 eMIOS200 A Register (EMIOS_CADR[n])
Depending on the mode of operation, internal registers A1 or A2, used for matches and captures, can be
assigned to address EMIOS_CADR[n]. A1 and A2 are cleared by reset. Table 28-9 summarizes the
EMIOS_CADR[n] writing and reading accesses for all operation modes. For more information see
Section 28.4.1.1, Unified Channel Modes of Operation.
28.3.2.6 eMIOS200 B Register (EMIOS_CBDR[n])
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address
EMIOS_CBDR[n]. Both B1 and B2 are cleared by reset. Table 28-9 summarizes the EMIOS_CBDR
writing and reading accesses for all operation modes. For more information see section Section 28.4.1.1,
Unified Channel Modes of Operation.
Depending on the channel configuration, it may have EMIOS_CBDR register or not. This means that if at
least one mode that requires the register is implemented, then the register is present. Otherwise, it is absent.
Offset: UC[n] base address + 0x0000 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
A
W
Reset0000000000000000
Figure 28-7. eMIOS200 A Register (EMIOS_CADR[n])
Offset: UC[n] base address + 0x0004 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
B
W
Reset0000000000000000
Figure 28-8. eMIOS200 B Register (EMIOS_CBDR[n])