FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-127
The FIFO control and configuration data are given in Section 26.6.3.7, Receive FIFO Control and
Configuration Data. The configuration of the FIFOs consists of two steps.
The first step is the allocation of the required amount of FlexRay memory for the FlexRay window. This
includes the allocation of the message buffer header area and the allocation of the message buffer data
fields. For more details see Section 26.6.4, FlexRay Memory Layout.
The second step is the programming of the configuration data register while the PE is in POC:config.
The following steps configure the layout of the FIFO.
• Configure the FIFO update and address modes in Module Configuration Register (MCR)
• Configure the FIFO system memory base address
• Configure the Receive FIFO Start Index Register (RFSIR) with the first message buffer header
index that belongs to the FIFO
• Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO entry size
• Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO depth
• Configure the FIFO Filters
26.6.9.3 FIFO Periodic Timer
The FIFO periodic timer is used to generate an FIFO almost-full interrupt at certain point in time, if the
almost-full watermark is not reached, but the FIFO is not empty. This can be used to prevent frames from
get stuck in the FIFO for a long time.
The FIFO periodic timer is configured via the Receive FIFO Periodic Timer Register (RFPTR). If the
periodic timer duration RFPTIR[PTD] is configured to 0x0000, the periodic timer is continuously expired.
If the periodic timer duration RFPTIR[PTD] is configured to 0x3FFF, the periodic timer never expires. If
the periodic timer is configured to a value ptd, greater than 0x0000 and smaller 0x3FFF, the periodic timer
expires and is restarted at the start of every communication cycle, and expires and is restarted after ptd
macroticks have been elapsed.
26.6.9.4 FIFO Reception
The FIFO reception is a controller internal operation.
A message frame reception is directed into the FIFO, if no individual message buffer is assigned for
transmission or subscribed for reception for the current slot. In this case the FIFO filter path shown in
Figure 26-138 is activated.
If the FIFO filter path indicates that the received frame has to be appended to the FIFO and the FIFO is
not full, the controller writes the received frame header into the message buffer header field indicated by
the controller internal FIFO write index. The frame payload data are written into the corresponding
message buffer data field. If the status of the received frame indicates a valid non-null frame, the slot status
information is written into the message buffer header field and the controller internal FIFO write index is
updated by 1 and the fifo fill level FLA (FLB) in the Receive FIFO Fill Level and POP Count Register
(RFFLPCR) is incremented.If the status of the received frame indicates an invalid or null frame, the frame
is not appended to the FIFO.
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