NXP Semiconductors PXN2020 - 36.10.1 Nexus2+;3 Auxiliary Port

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-105
The reset and ready pins that are often present as extensions to the JTAG port are not implemented.
Figure 36-81 shows the complete specification for the debug port in terms of pads.
Figure 36-81. Debug Port Pads
36.10.1 Nexus2+/3 Auxiliary Port
The N2+/3 port provides real-time development class 2+ and class 3 capabilities in compliance with the
IEEE-ISTO 5001-2003 standard. This development support is supplied without requiring external address
and data pins for internal visibility.
The Nexus pads are ready to be used for debug purposes only after the activation of the Nexus controller.
Such activation is consequent to a certain sequence given by the debugger.
MDO[9] N2+/3 Aux port Dedicated NO Dedicated
MDO[10] N2+/3 Aux port Dedicated NO Dedicated
MDO[11] N2+/3 Aux port Dedicated NO Dedicated
MSEO[0] N2+/3 Aux port Dedicated NO Dedicated
MSEO[1] N2+/3 Aux port Dedicated NO Dedicated
EVTO N2+/3 Aux port Dedicated
(could MUX with I/O)
YES
(MUX with I/O)
Dedicated
EVTI N2+/3Aux port Dedicated
(could MUX with I/O)
YES
(MUX with I/O)
Dedicated
Table 36-69. Pin/Pad Multiplexing
Pin Debug Port Multiplexed?
Available on
208 MPABGA
Available on
256 MAPBGA
JCOMP
TCK
TMS
TDI
TDO
EVTO
EVTI
EVTO
EVTI
MDO[11:0]
MCKO
MSEO[1:0]
JTAG
Optional
JTAG+
muxed
w/GPIO
(5 V pads)
Aux Nexus 2+/3 port
All packages
256 BGA only
3.3 V Fast Pads
Combined JTAG N2+/3 Port