NXP Semiconductors PXN2020 - 34.3.2.23 Conversion Timing Register 0 (CTR0); 34.3.2.24 Conversion Timing Register 1 (CTR1)

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
34-24 Freescale Semiconductor
34.3.2.23 Conversion Timing Register 0 (CTR0)
Conversion Timing Register 0 (CTR0) is associated with group 0 channels (channels 0–31). Parameters
contained in CTR0 are also used to perform Offset Cancellation and Offset Refresh.
34.3.2.24 Conversion Timing Register 1 (CTR1)
Conversion Timing Register 1 (CTR1) is associated with group 1 channels (channels 32–63).
Table 34-23. PSR2 Field Descriptions
Field Description
PRESn When set, presampling is enabled for channel n.
Address: Base + 0x0094 Access: User read/write
0 123456789101112131415
R0 000000000000000
W
Reset0 000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INP
LATCH
0
OFFSHIFT
0
INPCMP
0
INPSAMP
W
Reset0 000001000000011
Figure 34-24. Conversion Timing Register 0 (CTR0)
Table 34-24. CTR0 Field Descriptions
Field Description
INPLATCH Configuration bit for Latching phase duration.
0 Latching phase duration is one-half clock cycle.
1 Latching phase duration is one clock cycle.
Note: INPLATCH can be set only if INPCMP is bigger than 01b. Otherwise, INPLATCH is automatically set to
0 inside the ADC.
OFFSHIFT Configuration bits for the Offset Shift characteristic.
00 No shift (that is the transition between codes 000h and 001h) is reached when the Avin is equal to 1 LSB.
01 Transition between code 000h and 001h is reached when the Avin is equal to 1/2 LSB.
10 Transition between code 00h and 001h is reached when the Avin is equal to 0.
11 Reserved.
INPCMP Configuration bits for the comparison duration. See Table 34-27.
INPSAMP Configuration bits for the sampling phase duration. See Table 34-28.