Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
34-26 Freescale Semiconductor
Table 34-26. CTR2 Field Descriptions
Field Description
INPLATCH Configuration bit for Latching phase duration.
0b Latching phase duration is one-half clock cycle.
1b Latching phase duration is one clock cycle.
Note: The 1b condition is possible only if INPCMP is bigger than 01b. Otherwise, it is automatically set to 0b
inside the ADC.
INPCMP Configuration bits for the comparison duration. See Table 34-27.
INPSAMP Configuration bits for the sampling phase duration. See Table 34-28.
Table 34-27. Max AD_clk Frequency and Related Configuration Settings
INPLATCH INPCMP INPSAMPLE
AD_clk f
max
(MHz)
AD_clk Phase Min Duration
T
sample
min
(ns)
High Low
0 0b00 or 0b01 0b0000 0011 20 24 22.5 125
0 0b00 or 0b01 0b0000 0100 20 + 4% 24 22.5 168
1 0b10 0b0000 0100 20 + 4% 24 15 168
1 0b10 0b0000 0101 20 + 4% 15 15 135
1 0b11 0b0000 0110 32 + 4% 12 12 132
1 0b11 0b0000 0111 40 + 4% 9 9 128
1 0b11 0b0000 1000 50 + 4% 9 9 134
1 0b11 0b0000 1001 60 + 4% 7.5 7.5 128
Table 34-28. ADC Sampling and Conversion Timing
INPLATCH INPCMP INPSAMP T
sample
1
T
eval
ndelay T
conv
1 0b11 0b0000 1001 8 * Tck 30 * Tck 1 * Tck 39 * Tck
2
1 0b11 0b0000 1010 9 * Tck 30 * Tck 1 * Tck 40 * Tck
1 0b11 0b0000 1011 10 * Tck 30 * Tck 1 * Tck 41 * Tck
1 0b11 0b0000 1100 11 * Tck 30 * Tck 1 * Tck 42 * Tck
1 0b11 0b0000 1101 12 * Tck 30 * Tck 1 * Tck 43 * Tck
1 0b11 0b0000 1110 13 * Tck 30 * Tck 1 * Tck 44 * Tck
1 0b11 0b0000 1111 14 * Tck 30 * Tck 1 * Tck 45 * Tck
1 0b11 0b0001 0000 15 * Tck 30 * Tck 1 * Tck 46 * Tck
1 0b11 0b0001 0001 16 * Tck 30 * Tck 1 * Tck 47 * Tck
1 0b11 0b0001 0010 17 * Tck 30 * Tck 1 * Tck 48 * Tck
1 0b11 0b0001 0011 18 * Tck 30 * Tck 1 * Tck 49 * Tck
1 0b11 0b0001 0100 19 * Tck 30 * Tck 1 * Tck 50 * Tck
1 0b11 0b0001 0101 20 * Tck 30 * Tck 1 * Tck 51 * Tck
1 0b11 0b0001 0110 21 * Tck 30 * Tck 1 * Tck 52 * Tck
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