NXP Semiconductors PXN2020 - 26.6.18.5 Message Buffer Slot Status Field; 26.6.19 System Bus Access

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-146 Freescale Semiconductor
The increment condition for each slot status counter consists of two parts, the frame related condition part
and the slot related condition part. The internal slot status counter SSCRn_INT is incremented if at least
one of the conditions is fulfilled:
1. frame related condition:
• (SSCCRn.VFR | SSCCRn.SYF | SSCCRn.NUF | SSCCRn.SUF) // count on frame condition = 1;
and
• ((~SSCCRn.VFR | vSS!ValidFrame) & // valid frame restriction
(~SSCCRn.SYF | vRF!Header!SyFIndicator) & // sync frame indicator restriction
(~SSCCRn.NUF | ~vRF!Header!NFIndicator) & // null frame indicator restriction
(~SSCCRn.SUF | vRF!Header!SuFIndicator)) // startup frame indicator restriction = 1;
NOTE
The indicator bits SYF, NUF, and SUF are valid only when a valid frame
was received. Thus it is required to set the VFR always, whenever count on
frame condition is used.
2. slot related condition:
• ((SSCCRn.STATUSMASK[3] & vSS!ContentError) | // increment on content error
(SSCCRn.STATUSMASK[2] & vSS!SyntaxError) | // increment on syntax error
(SSCCRn.STATUSMASK[1] & vSS!BViolation) | // increment on boundary violation
(SSCCRn.STATUSMASK[0] & vSS!TxConflict)) // increment on transmission conflict = 1;
If the slot status counter is in single cycle mode (SSCCRn.MCY = 0), the internal slot status counter
SSCRn_INT is reset at each cycle start. If the slot status counter is in the multicycle mode
(SSCCRn.MCY = 1), the counter is not reset and incremented, until the maximum value is reached.
26.6.18.5 Message Buffer Slot Status Field
Each individual message buffer and each FIFO message buffer provides a slot status field, which provides
the information shown in Table 26-116 for the static/dynamic slot. The update conditions for the slot status
field depend on the message buffer type. Refer to the Message Buffer Update Sections in Section 26.6.6,
Individual Message Buffer Functional Description.
26.6.19 System Bus Access
This section provides a description of the system bus accesses performed by the controller.
All FlexRay memory data located in the system memory are accessed via the system bus. There are two
types of failures that can occur during the system bus access, the system bus illegal address access and the
system bus access timeout.
The behavior of the controller after the occurrence of a system bus failure is defined by the SBFF bit in
the Module Configuration Register (MCR).