Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
1-10 Freescale Semiconductor
• Retransmission from transmit FIFO following a collision (no system bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no system bus utilization)
• Address recognition
• RMON and IEEE statistics
• Interrupts for network activity and error conditions
NOTE
The FEC is available on the PXN21 only.
1.7.7 Analog to Digital Converter Module (ADC)
The PXN20 ADC features the following:
• 10-bit A/D resolution
• 0–V
DD
common mode conversion range
• Supports conversions speeds of up to 1 µs
• Internally multiplexed channels
— 10-bit 2 least significant bits (LSB) accuracy (TUE) available for 16 channels
— 10-bit 3 LSB accuracy (TUE) available for remaining channels
— Dedicated result register available for every internally muxed channel
• Externally multiplexed channels
— Internal control to support generation of external analog multiplexor selection
— Four internal channels optionally used to support externally multiplex inputs, providing
transparent control for additional ADC channels
— Each of the four channels supports up to 8 externally muxed inputs
• Three independently configurable sample and conversion times for high occurrence channels,
internally muxed channels and externally muxed channels
• Right-aligned result format
• Support for one-shot, scan and injection conversion modes
• Traceability of each channels with conversion result.
• Injection mode status bit implemented on adjacent 16-bit register for each result
• Independently configurable parameters for channels:
—Offset refresh
— Sampling
• Cross Triggering support (PXN21 only)
— Internal conversion triggering from periodic interrupt timer (PIT) or timed I/O module
(eMIOS200) via Cross Triggering Unit (CTU)
— One input pin configurable as external conversion trigger source
• Four configurable analog comparator channels offering range comparison with triggered alarm