Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-16 Freescale Semiconductor
To perform a read or write operation on the MII management interface, the MMFR register must be written
by the user. To generate a valid read or write management frame, the ST field must be written with a 01
pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame is
generated that does not comply with the IEEE 802.3 MII definition.
To generate an IEEE802.3-compliant MII management interface write frame (write to a PHY register),
the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern causes
the control logic to shift out the data in the MMFR register following a preamble generated by the control
state machine. During this time, the contents of the MMFR register are altered as the contents are serially
shifted and are unpredictable if read by the user. Once the write management frame operation has
completed, the MII interrupt is generated. At this time the contents of the MMFR register match the
original value written.
To generate an MII management interface read frame (read a PHY register) the user must write {01 10
PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a “don’t care”).
Writing this pattern causes the control logic to shift out the data in the MMFR register following a
preamble generated by the control state machine. During this time, the contents of the MMFR register are
altered as the contents are serially shifted, and are unpredictable if read by the user. Once the read
management frame operation has completed, the MII interrupt is generated. At this time, the contents of
the MMFR register match the original value written, except for the DATA field, whose contents have been
replaced by the value read from the PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents are altered.
Software should software should poll the EIR[MII] bit or use the EIR[MII] bit to generate an interrupt to
avoid writing to the MMFR register while frame generation is in progress.
25.3.4.8 MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (FEC_MDC signal) frequency, allows a preamble drop on
the MII management frame, and provides observability (intended for manufacturing test) of an internal
counter used in generating the FEC_MDC clock signal.
Table 25-9. MMFR Field Descriptions
Field Description
ST Start of frame delimiter. These bits must be programmed to 01 for a valid MII management frame.
OP Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a valid MII management
frame. A value of 11 produces “read” frame operation. A value of 00 produces “write” frame operation, but
these frames are not MII compliant.
PA PHY address. This field specifies one of as many as 32 attached PHY devices.
RA Register address. This field specifies one of as many as 32 registers within the specified PHY device.
TA Turn around. This field must be programmed to 10 to generate a valid MII management frame.
DATA Management frame data. This is the field for data to be written to or read from the PHY register.
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