Error Correction Status Module (ECSM)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 19-3
19.2.2 Register Descriptions
This section lists the ECSM registers in address order and describes the registers and their bit fields.
Attempted accesses to reserved addresses result in an error termination; however, attempted writes to
read-only registers are ignored and do not terminate with an error.
NOTE
Unless noted otherwise, writes to the programming model must match the
size of the register, e.g., an n-bit register only supports n-bit writes, etc.
Attempted writes of a different size than the register width produce an error
termination of the bus cycle and no change to the targeted register.
19.2.2.1 FEC Burst Optimization Master Control Register (FBOMCR)
The FEC burst optimization master control register (FBOMCR) controls FEC burst optimization behavior
on the system bus. Other FEC registers are described in Section 25.3.4.3, Ethernet Interrupt Mask Register
(EIMR), through Section 25.3.4.24, Receive Buffer Size Register (EMRBR).
In order to increase throughput, the FEC interface to the system bus can accumulate read requests or writes
to burst those transfers on the system bus. The FBOMCR determines the XBAR ports for which this
bursting is enabled, as well as whether the bursting is for reads, writes, or both. FBOMCR also controls
how errors for writes are handled.
0x000048 Reserved ECC error generation register (EEGR)
0x004C
Reserved
0x0050 PFlash ECC address register (PFEAR)
0x0054
Reserved
PFlash ECC master
register (PFEMR)
PFlash ECC attributes
register (PFEAT)
0x0058
Reserved
0x005C PFlash ECC Data register (PFEDR)
0x0060 PRAM ECC address register (PREAR)
0x0064
Reserved
PRAM ECC master
register (PREMR)
PRAM ECC attributes
register (PREAT)
0x0068
Reserved
0x006C PRAM ECC data register (PREDR)
Table 19-2. ECSM Graphical Memory Map
ECSM Offset
Register
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