Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-4 Freescale Semiconductor
25.1.3 Features
The FEC incorporates the following features:
• Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE802.3 MII
— 10-Mbps 7-wire interface (industry standard)
• Built-in FIFO and DMA controller
• IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition)
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• IEEE 802.3 full duplex flow control
• Support for full-duplex operation (200 Mbps throughput) with a system clock rate of 100 MHz
using the external FEC_TX_CLK or FEC_RX_CLK
• Support for half-duplex operation (100 Mbps throughput) with a system clock rate of 50 MHz
using the external FEC_TX_CLK or FEC_RX_CLK
• Retransmission from transmit FIFO following a collision (no system bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no system bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
• RMON and IEEE statistics
• Interrupts for network activity and error conditions
25.2 Modes of Operation
The primary operational modes are described in this section.
25.2.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point-to-point links between switches or end node to switch. Half
duplex mode is used in connections between an end node and a repeater or between repeaters. Selection
of the duplex mode is controlled by TCR[FDEN].
When configured for full duplex mode, flow control may be enabled. Refer to the TCR[RFC_PAUSE] and
TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and Section 25.4.10, Full Duplex Flow Control, for more
details.
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