NXP Semiconductors PXN2020 - 26.2.1.3 FR_A_TX_EN - Transmit Enable Channel A; 26.2.1.4 FR_B_RX - Receive Data Channel B; 26.2.1.5 FR_B_TX - Transmit Data Channel B; 26.2.1.6 FR_B_TX_EN - Transmit Enable Channel B

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-7
26.2.1.3 FR_A_TX_EN — Transmit Enable Channel A
The FR_A_TX_EN signal indicates to the FlexRay bus driver that the controller is attempting to transmit
data on channel A.
26.2.1.4 FR_B_RX — Receive Data Channel B
The FR_B_RX signal carries the receive data for channel B from the corresponding FlexRay bus driver.
26.2.1.5 FR_B_TX — Transmit Data Channel B
The FR_B_TX signal carries the transmit data for channel B to the corresponding FlexRay bus driver
26.2.1.6 FR_B_TX_EN — Transmit Enable Channel B
The FR_B_TX_EN signal indicates to the FlexRay bus driver that the controller is attempting to transmit
data on channel B.
26.2.1.7 FR_DBG[3], FR_DBG[2], FR_DBG[1] — , FR_DBG[0] — Strobe Signals
These signals provide the selected debug strobe signals. For details on the debug strobe signal selection
refer to Section 26.6.16, Strobe Signal Support.
26.3 Controller Host Interface Clocking
The clock for the CHI is derived from the system bus clock and has the same phase and frequency as the
system bus clock. Since the FlexRay protocol requires data delivery at fixed points in time, the memory
read cycles from the FlexRay memory must be finished after a fixed amount of time. To ensure this, a
minimum frequency f
chi
of the CHI clock is required, which is given in Equation 26-1.
Eqn. 26-1
Additional requirements for the minimum frequency of the CHI clock result from the number of message
buffers. These requirements are provided in Section 26.7.3, Number of Usable Message Buffers.
NOTE
If a complete message was transmitted from a transmit message buffer or
received into a message buffer and the controller host interface (CHI)
command FREEZE is issued by the application before the end of the current
slot, then this message buffer cannot be disabled and locked until the
module has entered the protocol state normal active. Consequently, this
message buffer cannot be disabled and locked by the application in the
protocol configuration state, which prevents the application from clearing
the commit bit CMT and the module from clearing the status bits. The
configuration bits in the Message Buffer Configuration, Control, Status
Registers (MBCCSRn) and the message buffer configuration registers
MBCCFRn, MBFIDRn, and MBIDXRn are not affected. At most one
message buffer per channel is affected.
f
chi
32MHz