Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-6 Freescale Semiconductor
28.2 External Signal Description
Refer to Table 3-1 and Section 3.4, Detailed Signal Description, for detailed signal descriptions.
Each channel has one external signal, eMIOS[n]. Through the pad configuration register
(SIU_PCRn[PA]), you can choose to have a pin’s function be the eMIOS channel in either or both places
as described in Table 28-6.
The output disable input [3:0] is provided to implement the output disable feature. They are connected to
emios_flag_out signals according to Section 28.2.2, Output Disable Input — eMIOS200 Output Disable
Input Signal.
28.2.1 eMIOS[n]
eMIOS[n] are the eMIOS channel pins. When used as input, an eMIOS[n] signal is available to be read by
the MCU through the EMIOS_CSRn[UCIN]. When used as output, eMIOS[n] signal is configured in the
unified channel status and control register (EMIOS_CSRn).
NOTE
All eMIOS channels support both input and output functions. When the
eMIOS function is the primary function of a pin, then both the input and
output functions are supported. When the eMIOS function is not the primary
function of the pin, then only the output functions are supported.
28.2.2 Output Disable Input — eMIOS200 Output Disable Input Signal
Output disable inputs are connected as defined in Table 28-2.
28.3 Memory Map and Register Description
This section provides a detailed description of all eMIOS200 registers.
28.3.1 Memory Map
The eMIOS200 memory map is shown in Table 28-3. The address of each register is given as an offset to
the eMIOS200 base address. Registers are listed in address order, identified by complete name and
mnemonic, and lists the type of accesses allowed.
Table 28-2. ODIS Input Signals
eMIOS200 channel Output Disable Input Signal
emios_flag_out[20] Output disable input[3]
emios_flag_out[19] Output disable input[2]
emios_flag_out[18] Output disable input[1]
emios_flag_out[17] Output disable input[0]
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