NXP Semiconductors PXN2020 - 10.5.2.1 Software Vector Mode; 10.5.2.2 Hardware Vector Mode

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-39
10.5.2.1 Software Vector Mode
interrupt_exception_handler:
code to create stack frame, save working register, and save SRR0 and SRR1
lis r3,INTC_IACKR_PRCn@ha # form adjusted upper half of INTC_IACKR_PRCn address
lwz r3,INTC_IACKR_PRCn@l(r3) # load INTC_IACKR_PRCn, which clears request to processor
lwz r3,0x0(r3) # load address of ISR from vector table
wrteei 1 # enable processor recognition of interrupts
code to save rest of context required by e500 EABI
mtlr r3 # move address of ISR into link register
blrl # branch to ISR; link register updated with epilog
# address
epilog:
code to restore most of context required by e500 EABI
# Popping the LIFO after the restoration of most of the context and the disabling of processor
# recognition of interrupts eases the calculation of the maximum stack depth at the cost of
# postponing the servicing of the next interrupt request.
mbar # ensure store to clear flag bit has completed
lis r3,INTC_EOIR_PRCn@ha # form adjusted upper half of INTC_EOIR address
li r4,0x0 # form 0 to write to INTC_EOIR_PRCn
wrteei 0 # disable processor recognition of interrupts
stw r4,INTC_EOIR_PRCn@l(r3) # store to INTC_EOIR_PRCn, informing INTC to lower priority
code to restore SRR0 and SRR1, restore working registers, and delete stack frame
rfi
vector_table_base_address:
address of ISR for interrupt with vector 0
address of ISR for interrupt with vector 1
.
.
.
address of ISR for interrupt with vector 510
address of ISR for interrupt with vector 511
ISRx:
code to service the interrupt event
code to clear flag bit which drives interrupt request to INTC
blr # return to epilog
10.5.2.2 Hardware Vector Mode
This interrupt exception handler is useful with processor and system bus implementations which support
a hardware vector. This example assumes that each
interrupt_exception_handlerx only has space for four
instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed.
interrupt_exception_handlerx:
b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue
interrupt_exception_handler_continuedx: