NXP Semiconductors PXN2020 - 32.1.3 Features

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 32-3
Figure 32-2. I
2
C Module DMA Interface Block Diagram
32.1.3 Features
The I
2
C has these major features:
• Compatible with I
2
C bus standard
• Multi-master operation
• Software programmable for one of 256 serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
Input
Sync
In/Out
Data
Shift
Register
Address
Compare
SDA
IRQAddress
Clock
Control
Start
Stop
Arbitration
Control
CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG
ADDR_DECODE DATA_MUX
Data bus
SCL
DMA request