General-Purpose Static RAM (SRAM)
PXN20 Microcontroller Reference Manual, Rev. 1
11-2 Freescale Semiconductor
Figure 11-2. Crossbar Arrangement Showing Embedded Memories (PXN21)
11.1.2 Features
Main features of the SRAM module are:
•PXN20
— Two separate RAM arrays implemented (592 KB total)
– 1 x 80 KB
– 1 x 512 KB
•PXN21
— One 128 KB RAM array implemented
• 64-bit RAM organization with ECC
• Available for data and program storage
• 64-bit ECC with single-bit correction, double-bit detection on a 32-bit boundary for data integrity
• Supports byte (8-bit), half word (16-bit), word (32-bit) and long word (64-bit) writes for optimal
use of memory
• User transparent ECC encoding and decoding for byte, half word, and word accesses
• Separate internal power domains applied RAM block Sleep modes to retain contents during low
power mode
• The device can boot from the RAM for fast recovery from low power mode without the need to
wait for the Flash to be available.
AHB Crossbar Switch
PFlash Controller
4 x 128
Page Buffer
SRAM
4 x 128
Page Buffer
Controller
SRAM
Controller
Peripheral
Bridge A
Peripheral
Bridge B
128 KB
2MB Flash
(with small blocks)
S0
64
S1
64
S2
64
S3
64
S4
64
S5
64
SRAM
(with ECC)
64
128
(ECC)
Memory Protection Unit
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