NXP Semiconductors PXN2020 - 31.3.2.1 eSCI Baud Rate Register (eSCI_BRR); 31.3.2.2 eSCI Control Register 1 (eSCI_CR1)

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-6 Freescale Semiconductor
31.3.2.1 eSCI Baud Rate Register (eSCI_BRR)
This register provides the control value for the serial baud rate. The baud rate and clock generation is
specified in Section 31.4.3, Baud Rate and Clock Generation.
A byte write access to only the upper byte of this register (eSCI_BRR[0:7]) will not change the content of
the register. Instead, the written byte is stored internally into a shadow register. A subsequent byte write
access to only the lower byte of this register (eSCI_BRR[8:15]) updates the lower byte and copies the
contents of the shadow register into the upper byte.
A byte write access to only the lower byte of this register (eSCI_BRR[8:0]) without a preceding byte write
access to only the upper byte copies a value of all zeroes into the upper byte.
A word write access to this register updates both the lower and upper byte immediately and is the
recommended write access type for this register.
31.3.2.2 eSCI Control Register 1 (eSCI_CR1)
This register provides bits to configure the functionality of the module, provides the interrupt enable bits
for the interrupt flags provided in the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) and provides
the control bits for the transmitter and receiver.
Offset: ESCI_BASE + 0x0000 Access: User read/write
0123456789101112131415
R0 0 0
SBR
W
Reset0000000000000100
Figure 31-2. eSCI Baud Rate Register (eSCI_BRR)
Table 31-2. eSCI_BRR Field Descriptions
Field Description
SBR Serial Baud Rate. This field provides the baud rate control value SBR.
Offset: ESCI_BASE + 0x0002 Access: User read/write
0123456789101112131415
R
LOOPS
0
RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK
W
Reset0000000000000000
Figure 31-3. eSCI Control Register 1 (eSCI_CR1)