NXP Semiconductors PXN2020 - 1.7.19 Interrupt Controller (INTC); 1.7.20 System Clocks and Clock Generation

Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
1-16 Freescale Semiconductor
1.7.19 Interrupt Controller (INTC)
The PXN20 implements an interrupt controller that features the following:
• Unique 9-bit vector for each of the 316 separate interrupt sources (22 reserved)
• 8 software triggerable interrupt sources
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Ability to modify the ISR or task priority.
— Modifying the priority can be used to implement the priority ceiling protocol for accessing
shared resources.
• External high priority interrupt directly accessing the main core critical interrupt mechanism
• Interrupt steering between main CPU and IOP
— Independent selection of any interrupt source to be routed through IOP
— Interrupts share same priority level between IOP and CPU
1.7.20 System Clocks and Clock Generation
The following list summarizes the system clock and clock generation on the PXN20:
• System clock can be derived from the following sources
— 4–40 MHz XTAL
—FMPLL
— 16 MHz IRC oscillator
• Programmable output clock divider of system clock (1, 2, 4, )
• Separate programmable peripheral bus clock divider ratio (1, 2, 4, ) applied to system clock
• Frequency Modulated Phase-locked loop (FMPLL)
— Input clock frequency from 4 MHz to 40 MHz
— Clock source from external oscillator
— Lock detect circuitry continuously monitors lock status
— Loss of clock (LOC) detection for reference and feedback clocks
— On-chip loop filter (for improved electromagnetic interference performance and reduces
number of external components required)
• On-chip crystal oscillatorsupporting 4 MHz to 40 MHz crystals
• Dedicated 16 MHz internal RC oscillator
— 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals
through selection as the system clock
— Used as default clock source out of reset
— Provides a clock for rapid start-up from low power modes
— Provides a clock for Software Watchdog Timer (SWT)
— Provides a back-up clock in the event of PLL or external oscillator clock failure
— 5% accuracy over the operating temperature range (after factory trim)