NXP Semiconductors PXN2020 - 31.4.3.1 Module Clock; 31.4.3.2 Transmitter Clock; 31.4.3.3 Receiver Clock

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-24 Freescale Semiconductor
The baud rate generator is enabled when the TE bit or RE bit in the eSCI Control Register 1 (eSCI_CR1)
is set to 1 for the first time. The baud rate generator is disabled when SBR = 0.
Baud rate generation is subject to one source of error:
• Integer division of the module clock may not give the exact required target baud rate.
Figure 31-19 lists some examples of achieving target baud rates with a module clock frequency of
MCLK = 10.2 MHz.
31.4.3.1 Module Clock
The module clock MCLK is derived from the system bus clock. It has the same phase and frequency.
31.4.3.2 Transmitter Clock
The transmitter clock TCLK is used to drive the data to the serial bus via the TXD pin. It is derived from
the system bus clock by the baud rate generator. The baud rate generator is controlled by the value of the
SBR[12:0] field in the eSCI Baud Rate Register (eSCI_BRR). The frequency of the transmitter clock is
determined by Equation 31-1 and defines the length of the transmitted bits, which is denoted as the bit
time.
Eqn. 31-1
31.4.3.3 Receiver Clock
The receiver clock RCLK is used to sample the data received on the RXD or TXD pin. It is derived from
the system bus clock by the baud rate generator. The baud rate generator is controlled by the value of the
SBR[12:0] field in the eSCI Baud Rate Register (eSCI_BRR). The frequency of the receiver sample clock
is determined by Equation 31-2.
Eqn. 31-2
Table 31-19. Baud Rates Error Example (MCLK = 10.2 MHz)
eSCI_BRR[SBR] RCLK (Hz) TCLK (Hz) Target Baud Rate Error (%)
17 600,000.0 37,500.0 38,400 2.3
33 309,090.9 19,318.2 19,200 .62
66 154,545.5 9659.1 9600 .62
133 76,691.7 4793.2 4800 .14
266 38,345.9 2396.6 2400 .14
531 19,209.0 1200.6 1200 .11
1062 9604.5 600.3 600 .05
2125 4800.0 300.0 300 .00
4250 2400.0 150.0 150 .00
5795 1760.1 110.0 110 .00
f
TCLK
f
MCLK
16 SBR 12:0
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=
f
RT
f
MCLK
SBR 12:0
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=