NXP Semiconductors PXN2020 - 8.3.2.38 Masked Parallel GPIO Pin Data Output Register 2 (SIU_MPGPDO2); 8.3.2.39 Masked Parallel GPIO Pin Data Output Register 3 (SIU_MPGPDO3)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-53
Writes to this register are coherent with the registers SIU_GPDO16_19, SIU_GPDO20_23,
SIU_GPDO24_27, and SIU_GPDO28_31.
8.3.2.38 Masked Parallel GPIO Pin Data Output Register 2 (SIU_MPGPDO2)
The SIU_MPGPDO2 register contains the masked parallel GPIO pin data output for PC[0:15].
Writes to this register are coherent with the registers SIU_GPDO32_35, SIU_GPDO36_39,
SIU_GPDO40_43, and SIU_GPDO44_47.
8.3.2.39 Masked Parallel GPIO Pin Data Output Register 3 (SIU_MPGPDO3)
The SIU_MPGPDO3 register contains the masked parallel GPIO pin data output for PD[0:15].
Writes to this register are coherent with the registers SIU_GPDO48_51, SIU_GPDO52_55,
SIU_GPDO56_59, and SIU_GPDO60_63.
Offset: SIU_BASE + 0x0C84 Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PB_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PB[0:15]
Reset0000000000000000
Figure 8-45. Masked Parallel GPIO Pin Data Output Register 1 (SIU_MPGPDO1)
Offset: SIU_BASE + 0x0C88 Access: User write-only
0 1 2 3 4 5 6 7 8 9 101112131415
R0000000000000000
W PC_MASK[0:15]
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W PC[0:15]
Reset0000000000000000
Figure 8-46. Masked Parallel GPIO Pin Data Output Register 2 (SIU_MPGPDO2)