NXP Semiconductors PXN2020 - 31.4.7.2 Interrupt Request Generation; 31.5 Application Information; 31.5.1 SCI Data Frames Separated by Preamble

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-52 Freescale Semiconductor
31.4.7.2 Interrupt Request Generation
The eSCI module provides one hardware interrupt request signal to the systems interrupt controller. This
interrupt request signal is asserted if and only if at least one of the interrupt flags and the corresponding
interrupt enables are set to 1. Otherwise the interrupt line is deasserted.
31.5 Application Information
31.5.1 SCI Data Frames Separated by Preamble
To separate SCI data frame with preambles with minimum idle line time, use this sequence between
messages:
1. Write to the eSCI SCI Data Register (eSCI_SDR).
— This sets the internal iCMT bit, which requests the data transmission.
2. Wait until TDRE in the eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set.
— This indicates the start of transmission; the iCMT bit was cleared.
3. Clear and subsequently set the TE bit in the eSCI Control Register 1 (eSCI_CR1).
— This set the internal iPRE bit, which requests the preamble transmission.
4. Write to the eSCI SCI Data Register (eSCI_SDR).
— This sets the internal iCMT bit, which requests the data transmission.
Receiver SCI eSCI_IFSR1[OR] eSCI_CR2[ORIE]
Receiver SCI, LIN eSCI_IFSR1[NF] eSCI_CR2[NFIE]
Receiver SCI, LIN eSCI_IFSR1[FE] eSCI_CR2[FEIE]
Receiver SCI eSCI_IFSR1[PF] eSCI_CR2[PFIE]
Receiver LIN eSCI_IFSR1[BERR] eSCI_CR2[BERRIE]
Receiver LIN eSCI_IFSR2[RXRDY] eSCI_LCR1[RXIE]
Transmitter LIN eSCI_IFSR2[TXRDY] eSCI_LCR1[TXIE]
Receiver LIN eSCI_IFSR2[LWAKE] eSCI_LCR1[WUIE]
Receiver LIN eSCI_IFSR2[STO] eSCI_LCR1[STIE]
Receiver LIN eSCI_IFSR2[PBERR] eSCI_LCR1[PBIE]
Receiver LIN eSCI_IFSR2[CERR] eSCI_LCR1[CIE]
Receiver LIN eSCI_IFSR2[CKERR] eSCI_LCR1[CKIE]
Receiver LIN eSCI_IFSR2[FRC] eSCI_LCR1[FCIE]
Receiver LIN eSCI_IFSR2[UREQ] eSCI_LCR2[URIE]
Transmitter, Receiver LIN eSCI_IFSR2[OVFL] eSCI_LCR2[OFIE]
Table 31-33. eSCI Interrupt Flags and Interrupt Enable Bits (continued)
Interrupt Source Interrupt Flag Interrupt Enable Interrupt Enable Bit