FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-129
26.6.9.8.1 FIFO Interrupt Flag Update
Th FIFO Interrupt Flag Update mode is configured, when the FIFO update mode flag MCR[FUM] is set
to 0. In this mode FIFOA (FIFOB) will be updated by 1 entry, when the interrupt flag GIFER[FAFAIF]
(GIFER[FAFBIF]) is written with 1 by the application.
If the FIFO is empty, the update request is ignored without any notification.
The read index in the Receive FIFO A Read Index Register (RFARIR) (Receive FIFO B Read Index
Register (RFBRIR)) is incremented by 1, if the FIFO was not empty. If the read index reaches the top of
the FIFO, it wraps around to the FIFO start index automatically.
26.6.9.9 FIFO Filtering
The FIFO filtering is activated after all enabled individual receive message buffers have been searched
without success for a message buffer to receive the current frame.
The controller provides three sets of FIFO filters. The FIFO filters are applied to valid non-null frames
only. The FIFO will not receive invalid or null-frames. For each FIFO filter, the pass criteria is specified
in the related section given below. Only frames that have passed all filters will be appended to the FIFO.
The FIFO filter path is depicted in Figure 26-138.
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