NXP Semiconductors PXN2020 - 10.4.3.2 Hardware Vector Mode Handshaking

Interrupts and Interrupt Controller (INTC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 10-37
Figure 10-20. Software Vector Mode Handshaking Timing Diagram
10.4.3.2 Hardware Vector Mode Handshaking
A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode and
handshaking near the end of the interrupt exception handler is shown in Figure 10-21. As in software
vector mode, the INTC examines the peripheral and software settable interrupt requests and, when it finds
one asserted with a higher priority than PRI in the associated INTC_CPR_PRC0 or INTC_CPR_PRC1, it
asserts the interrupt request to the associated processor. The INTVEC field in the associated
INTC_IACKR_PRC0 or INTC_IACKR_PRC1 is updated with the preempting peripheral or software
settable interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC
field retains that value until the next time the interrupt request to the associated processor is asserted. In
addition, the value of the interrupt vector to the associated processor also matches the value of the
INTVEC field in the associated INTC_IACKR_PRC0 or INTC_IACKR_PRC1. The rest of the
handshaking process is described in Section 10.1.3.2, Hardware Vector Mode.
The handshaking near the end of the interrupt exception handler, that is written to the associated
INTC_EOIR_PRC0 or INTC_EOIR_PRC1, is the same as in software vector mode (see
Section 10.4.3.1.2, End of Interrupt Exception Handler).
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR_PCRn
Write
INTC_EOIR_PCRn
INTVEC in
INTC_IACKR_PCRn
PRI in
INTC_CPR_PCRn
Peripheral Interrupt
Request 100
0
0
0
108
10