FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-8 Freescale Semiconductor
To avoid this,
• The application should not send the CHI command FREEZE and use the
CHI command HALT instead.
• Before sending the CHI command FREEZE the application should
repeatedly disable all message buffers until all message buffers are
disabled. This maximum duration of this task is three static or three
dynamic slots.
26.4 Protocol Engine Clocking
The clock for the protocol engine can be generated by two sources. The first source is the internal crystal
oscillator and the second source is an internal PLL. The clock source to be used is selected by the clock
source select bit CLKSEL in the Module Configuration Register (MCR).
26.4.1 Oscillator Clocking
If the protocol engine is clocked by the internal crystal oscillator, a 40 MHz crystal or CMOS compatible
clock must be connected to the oscillator pins. The crystal or clock must fulfill the requirements given by
the FlexRay Communications System Protocol Specification, Version 2.1 Rev A.
26.4.2 PLL Clocking
26.5 Memory Map and Register Description
The controller occupies 1280 bytes of address space starting at the controller’s base address defined by the
memory map of the MCU.
26.5.1 Memory Map
The complete memory map of the controller is shown in Table 26-3. The addresses presented here are the
offsets relative to the controller base address which is defined by the MCU address map.
Table 26-3. FlexRay Memory Map
Offset Register Access
Module Configuration and Control
0x0000 Module Version Register (MVR) R
0x0002 Module Configuration Register (MCR) R/W
0x0004 System Memory Base Address High Register (SYMBADHR) R/W
0x0006 System Memory Base Address Low Register (SYMBADLR) R/W
0x0008 Strobe Signal Control Register (STBSCR) R/W
0x000A Reserved R
0x000C Message Buffer Data Size Register (MBDSR) R/W
0x000E Message Buffer Segment Size and Utilization Register (MBSSUTR) R/W
Test Registers
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