Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-36 Freescale Semiconductor
29.4.7.4 Protocol Timing
The clock source to the CAN protocol interface (CPI) can be either the system clock or a direct feed from
the oscillator pin EXTAL. The clock source is selected by the CLK_SRC bit in the CANx_CTRL. The
clock is fed to the prescaler to generate the serial clock (SCK).
The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the
CAN protocol. The CANx_CTRL has various fields used to control bit timing parameters: PRESDIV,
PROPSEG, PSEG1, PSEG2 and RJW. See Section 29.3.4.2, Control Register (CANx_CTRL).
The PRESDIV field controls a prescaler that generates the serial clock (SCK), whose period defines the
‘time quantum’ used to compose the CAN waveform. A time quantum is the atomic unit of time handled
by FlexCAN.
A bit time is subdivided into three segments
1
(reference Figure 29-16 and Table 29-17):
• SYNCSEG: This segment has a fixed length of one time quantum. Signal edges are expected to
happen within this section.
• Time segment 1: This segment includes the propagation segment and the phase segment 1 of the
CAN standard. It can be programmed by setting the PROPSEG and the PSEG1 fields of the
CANx_CTRL register so that their sum (plus 2) is in the range of 4 to 16 time quanta.
• Time segment 2: This segment represents the phase segment 2 of the CAN standard. It can be
programmed by setting the PSEG2 field of the CANx_CTRL register (plus 1) to be 2 to 8 time
quanta long.
1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch
CAN 2.0A/B protocol specification dated September 1991 for bit timing.
f
Tq
f
CANCLK
Prescaler Value
------------------------------------------=
Bit Rate
f
Tq
Number of Time Quanta
---------------------------------------------------------------------=
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