NXP Semiconductors PXN2020 - 32.5.2 DMA Application Information; 32.5.2.1 DMA Mode, Master Transmit

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
32-20 Freescale Semiconductor
32.5.2 DMA Application Information
The DMA interface on the I
2
C is not completely autonomous and requires intervention from the CPU to
start and to terminate the frame transfer. DMA mode is valid for master-transmit and master-receive modes
only. Software must ensure that the DMA enable bit in the control register is not set when the I
2
C module
is configured in master mode.
The DMA controller must transfer only one byte of data per Tx/Rx request. This is because there is no
FIFO on the I
2
C block.
The CPU should also keep the I
2
C interrupt enabled during a DMA transfer to detect the arbitration lost
condition and take action to recover from this situation. The DMAEN bit in the IBCR register works as a
disable for the transfer complete interrupt. This means that during normal transfers (no errors) there always
is either an interrupt or a request to the DMA controller, depending on the setting of the DMAEN bit. All
error conditions trigger an interrupt and require CPU intervention. The address match condition does not
occur in DMA mode as the I
2
C should never be configured for slave operation.
The following sections detail how to set up a DMA transfer and what intervention is required from the
CPU. It is assumed that the system DMA controller is capable of generating an interrupt after a certain
number of DMA transfers have taken place.
32.5.2.1 DMA Mode, Master Transmit
Figure 32-14 details exactly the operation for using a DMA controller to transmit n data bytes to a slave.
The first byte (the slave calling address) is always transmitted by the CPU. All subsequent data bytes (apart
from the last data byte) can be transferred by the DMA controller. The last data byte must be transferred
by the CPU.