NXP Semiconductors PXN2020 - 8.3.2.58 eMIOS Select Register for DSPI_C (SIU_EMIOSC); 8.3.2.59 SIU_DSPICH;L Select Register for DSPI_C (SIU_DSPICHLC)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-65
8.3.2.58 eMIOS Select Register for DSPI_C (SIU_EMIOSC)
The SIU_EMIOSC register selects the output serialized source for the DSPI_C channel.
8.3.2.59 SIU_DSPICH/L Select Register for DSPI_C (SIU_DSPICHLC)
The SIU_DSPICHLC register enables the data path from the Masked Serial GPO register for DSPI_C to
the equivalent bit position in the DSPI_C channel frame.
Table 8-44. SIU_DSPIBHLB Field Descriptions
Field Description
DSPIBHn Data Path Enable for DSPI_B High.
0 Data path disabled to DSPI_B High.
1 Data path enabled to DSPI_B High.
DSPIBLn Data Path Enable for DSPI_B Low.
0 Data path disabled to DSPI_B Low.
1 Data path enabled to DSPI_B Low.
Offset: SIU_BASE + 0x0D64 Access: User read/write
0123456789101112131415
R
EMIOS
31
EMIOS
30
EMIOS
29
EMIOS
28
EMIOS
27
EMIOS
26
EMIOS
25
EMIOS
24
EMIOS
23
EMIOS
22
EMIOS
21
EMIOS
20
EMIOS
19
EMIOS
18
EMIOS
17
EMIOS
16
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EMIOS
15
EMIOS
14
EMIOS
13
EMIOS
12
EMIOS
11
EMIOS
10
EMIOS
9
EMIOS
8
EMIOS
7
EMIOS
6
EMIOS
5
EMIOS
4
EMIOS
3
EMIOS
2
EMIOS
1
EMIOS
0
W
Reset0000000000000000
Figure 8-66. eMIOS Select Register for DSPI_C (SIU_EMIOSC)
Table 8-45. SIU_EMIOSC Field Descriptions
Field Description
EMIOSn eMIOS Channel Enable.
0 This eMIOS channel is not enabled.
1 This eMIOS channel is enabled.