General-Purpose Static RAM (SRAM)
PXN20 Microcontroller Reference Manual, Rev. 1
11-6 Freescale Semiconductor
• Power-on reset
• Low-voltage inhibit (LVI) reset
• External reset
• PLL loss of clock (if enabled)
• PLL loss of lock (if enabled)
The user code must re-initialize the RAM after any of the above resets; otherwise, an ECC event might
occur.
11.6 DMA Requests
There are no DMA requests associated with the system SRAM.
11.7 Interrupt Requests
There are no interrupt requests associated with the system SRAM, except for the ECC reporting through
the MCM module.
11.8 Initialization and Application Information
To use the SRAM, the ECC must check all bits that require initialization after power on. Use a 64-bit
cache-inhibited write to each SRAM location to initialize the SRAM array as part of the application
initialization code. All writes must specify an even number of registers performed on 64-bit word-aligned
boundaries. If the write is not the entire 64 bits (e.g., 8, 16, or 32 bits), a read / modify / write operation is
generated that checks the ECC value upon the read. Refer to Section 11.5, SRAM ECC Mechanism.
NOTE
You must initialize SRAM, even if the application does not use ECC
reporting.
11.8.1 Example Code
To initialize SRAM correctly, use a store multiple word (stmw) instruction to implement 64-bit writes to
all SRAM locations. The stmw instruction concatenates two 32-bit registers to implement a single 64-bit
write. To ensure the writes are 64-bits, specify an even number of registers and write on 64-bit
word-aligned boundaries.
The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits.
Example 11-1. Initializing SRAM ECC Bits
init_RAM:
lis r11,0x4000 # base address of the SRAM, 64-bit word aligned
ori r11,r11,0 # not needed for this address but could be for others
li r12,640 # loop counter to get all of SRAM;
# 80k/4 bytes/32 GPRs = 640
mtctr r12
init_ram_loop:
stmw r0,0(r11) # write all 32 GPRs to SRAM
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