Home
NXP Semiconductors
Controller
PXN2020
Page 325
NXP Semiconductors PXN2020 - Page 325
1376 pages
Manual
To Next Page
To Next Page
To Previous Page
To Previous Page
Loading...
General-Purpose Static RAM (SRAM)
PXN20 Microcontr
oller Reference Manual, Rev
. 1
F
reescale
Semiconductor
11-7
addi
r11,r11,128
# inc the ram ptr; 32 GP
Rs * 4 bytes = 128?
bdnz
init_ram_loop
# loop for 80k of SRAM
324
326
Table of Contents
Main Page
PXN20 Microcontroller Reference Manual
1
About This Book
33
Suggested Reading
35
Chapter 1 Introduction
43
1.1 Overview
43
1.2 PXN20 Features
43
1.3 PXN20 Block Diagram
45
1.4 PXN21 Block Diagram
46
1.5 Critical Performance Parameters
47
1.5.1 Low Power Operation
47
1.6 Packages
48
1.7 Module Features
48
1.7.1 High Performance e200z650 Core Processor (CPU)
48
1.7.2 I/O Processor High Performance e200z0 Core (IOP)
49
1.7.3 On-Chip Flash
49
1.7.4 On-Chip SRAM
51
1.7.5 On-Chip Voltage Regulator (VREG)
51
1.7.6 Fast Ethernet Controller (FEC)
51
1.7.7 Analog to Digital Converter Module (ADC)
52
1.7.8 Cross Triggering Unit (CTU)
53
1.7.9 Serial Communication Interface Module (UART)
53
1.7.10 Controller Area Network Module (CAN)
54
1.7.11 Inter-IC Communications Module (I2C)
55
1.7.12 Serial Peripheral Interface Module (SPI)
55
1.7.13 Enhanced Modular Input Output System (Timers - eMIOS200)
56
1.7.14 Periodic Interrupt Timer Module (PIT)
56
1.7.15 System Timer Module (STM)
56
1.7.16 Enhanced Direct Memory Access Controller (eDMA)
57
1.7.17 Crossbar Switch (XBAR)
57
1.7.18 Memory Protection Unit (MPU)
57
1.7.19 Interrupt Controller (INTC)
58
1.7.20 System Clocks and Clock Generation
58
1.7.21 System Integration Unit (SIU)
59
1.7.22 Software Watchdog Timer (SWT)
59
1.7.23 Boot Assist Module (BAM)
59
1.7.24 Dual-Channel FlexRay Controller (FR)
60
1.7.25 Media Local Bus (MLB)
61
1.7.26 Real Time Counter (RTC)
61
1.7.27 JTAG Controller (JTAGC)
61
1.7.28 Nexus Development Interface (NDI)
62
1.8 Developer Support
63
Chapter 2 Memory Map
65
2.1 Introduction
65
Chapter 3 Signal Description
69
3.1 Introduction
69
3.2 Signal Properties Summary
69
3.2.1 I/O Power and Ground Segmentation
86
3.3 Pinout
87
3.4 Detailed Signal Description
89
3.4.1 Port A Pins
89
3.4.1.1 PA0 to PA13 - GPI (PA[0:13]) / Analog Input (AN[0:13])
89
3.4.1.2 PA14 - GPI (PA[14]) / Analog Input (AN[14]) / 32 kHz Crystal Input (EXTAL32)
89
3.4.1.3 PA15 - GPI (PA[15]) / Analog Input (AN[15]) / 32 kHz Crystal Output (XTAL32)
89
3.4.2 Port B Pins
89
3.4.2.1 PB0 - GPIO (PB[0]) / Analog Input (AN[16]) / Analog Input Channel for External Mux (ANW)
89
3.4.2.2 PB1 - GPIO (PB[1]) / Analog Input (AN[17]) / Analog Input Channel for External Mux (ANX)
89
3.4.2.3 PB2 - GPIO (PB[2]) / Analog Input (AN[18]) / Analog Input Channel for External Mux (ANY)
89
3.4.2.4 PB3 - GPIO (PB[3]) / Analog Input (AN[19]) / Analog Input Channel for External Mux (ANZ)
90
3.4.2.5 PB4 to PB7 - GPIO (PB[4:7]) / Analog Input (AN[20:23])
90
3.4.2.6 PB8 - GPIO (PB[8]) / Analog Input (AN[24]) / DSPI_A Peripheral Chip Select (PCS_A[2])
90
3.4.2.7 PB9 - GPIO (PB[9]) / Analog Input (AN[25]) / DSPI_A Peripheral Chip Select (PCS_A[3])
90
3.4.2.8 PB10 - GPIO (PB[10]) / Analog Input (AN[26]) / DSPI_B Peripheral Chip Select (PCS_B[4])
90
3.4.2.9 PB11 - GPIO (PB[11]) / Analog Input (AN[27]) / DSPI_B Peripheral Chip Select (PCS_B[5])
90
3.4.2.10 PB12 - GPIO (PB[12]) / Analog Input (AN[28]) / DSPI_C Peripheral Chip Select (PCS_C[1])
90
3.4.2.11 PB13 - GPIO (PB[13]) / Analog Input (AN[29]) / DSPI_C Peripheral Chip Select (PCS_C[2])
90
3.4.2.12 PB14 - GPIO (PB[14]) / Analog Input (AN[30]) / DSPI_D Peripheral Chip Select (PCS_D[3])
91
3.4.2.13 PB15 - GPIO (PB[15]) / Analog Input (AN[31]) / DSPI_D Peripheral Chip Select (PCS_D[4])
91
3.4.3 Port C Pins
91
3.4.3.1 PC0 to PC1 - GPIO (PC[0:1]) / Analog Input (AN[32:33])
91
3.4.3.2 PC2 - GPIO (PC[2]) / Analog Input (AN[34]) / Nexus Event In (EVTI)
91
3.4.3.3 PC3 - GPIO (PC[3]) / Analog Input (AN[35]) / Nexus Event Out (EVTO)
91
3.4.3.4 PC4 - GPIO (PC[4]) / Analog Input (AN[36])
91
3.4.3.5 PC5 - GPIO (PC[5]) / Analog Input (AN[37]) / Z6 Non-Maskable Interrupt (Z6_NMI)
91
3.4.3.6 PC6 - GPIO (PC[6]) / Analog Input (AN[38]) / Z0 Non-Maskable Interrupt (Z0_NMI)
91
3.4.3.7 PC7 - GPIO (PC[7]) / Analog Input (AN[39]) / FlexRay Debug 3 (FR_DBG[3])
91
3.4.3.8 PC8 - GPIO (PC[8]) / Analog Input (AN[40]) / FlexRay Debug 2 (FR_DBG[2])
92
3.4.3.9 PC9 - GPIO (PC[9]) / Analog Input (AN[41]) / FlexRay Debug 1 (FR_DBG[1])
92
3.4.3.10 PC10 - GPIO (PC[10]) / Analog Input (AN[42]) / FlexRay Debug 0 (FR_DBG[0])
92
3.4.3.11 PC11 - GPIO (PC[11]) / Analog Input (AN[43]) / I2C_C Serial Clock Line (SCL_C)
92
3.4.3.12 PC12 - GPIO (PC[12]) / Analog Input (AN[44]) / I2C_C Serial Data Line (SDA_C)
92
3.4.3.13 PC13 - GPIO (PC[13]) / Analog Input (AN[45]) / External Analog Mux Address Output (MA[0])
92
3.4.3.14 PC14 - GPIO (PC[14]) / Analog Input (AN[46]) / External Analog Mux Address Output (MA[1])
92
3.4.3.15 PC15 - GPIO (PC[15]) / Analog Input (AN[47]) / External Analog Mux Address Output (MA[2])
92
3.4.4 Port D Pins
93
3.4.4.1 PD0 - GPIO (PD[0]) / CAN_A Transmit (CNTX_A)
93
3.4.4.2 PD1 - GPIO (PD[1]) / CAN_A Receive (CNRX_A)
93
3.4.4.3 PD2 - GPIO (PD[2]) / CAN_B Transmit (CNTX_B)
93
3.4.4.4 PD3 - GPIO (PD[3]) / CAN_B Receive (CNRX_B)
93
3.4.4.5 PD4 - GPIO (PD[4]) / CAN_C Transmit (CNTX_C)
93
3.4.4.6 PD5 - GPIO (PD[5]) / CAN_C Receive (CNRX_C)
93
3.4.4.7 PD6 - GPIO (PD[6]) / CAN_D Transmit (CNTX_D) / TXD_K / I2C_B Serial Clock Line (SCL_B)
93
3.4.4.8 PD7 - GPIO (PD[7]) / CAN_D Receive (CNRX_D) / RXD_K / I2C_B Serial Data Line (SDA_B)
93
3.4.4.9 PD8 - GPIO (PD[8]) / CAN_E Transmit (CNTX_E) / TXD_LK / I2C_C Serial Clock Line (SCL_C)
93
3.4.4.10 PD9 - GPIO (PD[9]) / CAN_E Receive (CNRX_E) / RXD_L / I2C_C Serial Data Line (SDA_C)
94
3.4.4.11 PD10 - GPIO (PD[10]) / CAN_F Transmit (CNTX_F) / TXD_M / I2C_D Serial Clock Line (SCL_D)
94
3.4.4.12 PD11 - GPIO (PD[11]) / CAN_F Receive (CNRX_F) / RXD_M / I2C_D Serial Data Line (SDA_D)
94
3.4.4.13 PD12 - GPIO (PD[12]) / eSCI_A Transmit (TXD_A)
94
3.4.4.14 PD13 - GPIO (PD[13]) / eSCI_A Receive (RXD_A)
94
3.4.4.15 PD14 - GPIO (PD[14]) / eSCI_B Transmit (TXD_B)
94
3.4.4.16 PD15 - GPIO (PD[15]) / eSCI_B Receive (RXD_B)
94
3.4.5 Port E Pins
94
3.4.5.1 PE0 - GPIO (PE[0]) / eSCI_C Transmit (TXD_C) / eMIOS Channel (eMIOS[31])
94
3.4.5.2 PE1 - GPIO (PE[1]) / eSCI_C Receive (RXD_C) / eMIOS Channel (eMIOS[30])
95
3.4.5.3 PE2 - GPIO (PE[2]) / eSCI_D Transmit (TXD_D) / eMIOS Channel (eMIOS[29])
95
3.4.5.4 PE3 - GPIO (PE[3]) / eSCI_D Receive (RXD_D) / eMIOS Channel (eMIOS[28])
95
3.4.5.5 PE4 - GPIO (PE[4]) / eSCI_E Transmit (TXD_E) / eMIOS Channel (eMIOS[27])
95
3.4.5.6 PE5 - GPIO (PE[5]) / eSCI_E Receive (RXD_E) / eMIOS Channel (eMIOS[26])
95
3.4.5.7 PE6 - GPIO (PE[6]) / eSCI_F Transmit (TXD_F) / eMIOS Channel (eMIOS[25])
95
3.4.5.8 PE7 - GPIO (PE[7]) / eSCI_F Receive (RXD_F) / eMIOS Channel (eMIOS[24])
95
3.4.5.9 PE8 - GPIO (PE[8]) / eSCI_G Transmit (TXD_G) / DSPI_A Peripheral Chip Select (PCS_A[1])
96
3.4.5.10 PE9 - GPIO (PE[9]) / eSCI_G Receive (RXD_G) / DSPI_A Peripheral Chip Select (PCS_A[4])
96
3.4.5.11 PE10 - GPIO (PE[10]) / eSCI_H Transmit (TXD_H) / DSPI_B Peripheral Chip Select (PCS_B[3])
96
3.4.5.12 PE11 - GPIO (PE[11]) / eSCI_H Receive (RXD_H) / DSPI_B Peripheral Chip Select (PCS_B[2])
96
3.4.5.13 PE12 - GPIO (PE[12]) / eSCI_J Transmit (TXD_J) / DSPI_C Peripheral Chip Select (PCS_C[5])
96
3.4.5.14 PE13 - GPIO (PE[13]) / eSCI_J Receive (RXD_J) / DSPI_C Peripheral Chip Select (PCS_C[3])
96
3.4.5.15 PE14 - GPIO (PE[14]) / I2C_A Serial Clock Line (SCL_A) / DSPI_D Peripheral Chip Select (PCS_D[2])
96
3.4.5.16 PE15 - GPIO (PE[15]) / I2C_A Serial Data Line (SDA_A) / DSPI_D Peripheral Chip Select (PCS_D[5])
97
3.4.6 Port F Pins
97
3.4.6.1 PF0 - GPIO (PF[0]) / DSPI_A Clock (SCK_A)
97
3.4.6.2 PF1 - GPIO (PF[1]) / DSPI_A Data Output (SOUT_A)
97
3.4.6.3 PF2 - GPIO (PF[2]) / DSPI_A Data Input (SIN_A)
97
3.4.6.4 PF3 - GPIO (PF[3]) / DSPI_A Peripheral Chip Select (PCS_A[0]) / DSPI_B Peripheral Chip Select (PCS_B[5]) / DSPI_C Peripheral Chip Select (PCS_C[4])
97
3.4.6.5 PF4 - GPIO (PF[4]) / DSPI_B Clock (SCK_B) / DSPI_A Peripheral Chip Select (PCS_A[1]) / DSPI_C Peripheral Chip Select (PCS_C[2])
97
3.4.6.6 PF5 - GPIO (PF[5]) / DSPI_B Data Output (SOUT_B) / DSPI_A Peripheral Chip Select (PCS_A[2]) / DSPI_C Peripheral Chip Select (PCS_C[3])
97
3.4.6.7 PF6 - GPIO (PF[6]) / DSPI_B Data Input (SIN_B) / DSPI_A Peripheral Chip Select (PCS_A[3]) / DSPI_C Peripheral Chip Select (PCS_C[5])
98
3.4.6.8 PF7 - GPIO (PF[7]) / DSPI_B Peripheral Chip Select (PCS_B[0]) / DSPI_C Peripheral Chip Select / (PCS_C[5]) / DSPI_D Peripheral Chip Select (PCS_D[4])
98
3.4.6.9 PF8 - GPIO (PF[8]) / DSPI_C Clock (SCK_C)
98
3.4.6.10 PF9 - GPIO (PF[9]) / DSPI_C Data Output (SOUT_C)
98
3.4.6.11 PF10 - GPIO (PF[10]) / DSPI_C Data Input (SIN_C)
98
3.4.6.12 PF11 - GPIO (PF[11]) / DSPI_C Peripheral Chip Select (PCS_C[0]) / DSPI_D Peripheral Chip Select / (PCS_D[5]) / DSPI_A Peripheral Chip Select (PCS_A[4])
98
3.4.6.13 PF12 - GPIO (PF[12]) / DSPI_D Clock (SCK_D)
98
3.4.6.14 PF13 - GPIO (PF[13]) / DSPI_D Data Output (SOUT_D)
98
3.4.6.15 PF14 - GPIO (PF[14]) / DSPI_D Data Input (SIN_D)
99
3.4.6.16 PF15 - GPIO (PF[15]) / DSPI_D Peripheral Chip Select (PCS_D[0]) / DSPI_A Peripheral Chip Select (PCS_A[5]) / DSPI_B Peripheral Chip Select (PCS_B[4])
99
3.4.7 Port G Pins
99
3.4.7.1 PG0 - GPIO (PG[0]) / DSPI_A Peripheral Chip Select (PCS_A[4]) / DSPI_B Peripheral Chip Select (PCS_B[3]) / Analog Input (AN[48])
99
3.4.7.2 PG1 - GPIO (PG[1]) / DSPI_A Peripheral Chip Select (PCS_A[5]) / DSPI_B Peripheral Chip Select (PCS_B[4]) / Analog Input (AN[49])
99
3.4.7.3 PG2 - GPIO (PG[2]) / DSPI_D Peripheral Chip Select (PCS_D[1]) / I2C_C Serial Clock Line (SCL_C) / Analog Input (AN[50])
99
3.4.7.4 PG3 - GPIO (PG[3]) / DSPI_D Peripheral Chip Select (PCS_D[2]) / I2C_C Serial Data Line (SDA_C) / Analog Input (AN[51])
99
3.4.7.5 PG4 - GPIO (PG[4]) / DSPI_D Peripheral Chip Select (PCS_D[3]) / I2C_B Serial Clock Line (SCL_B) / Analog Input (AN[52])
99
3.4.7.6 PG5 - GPIO (PG[5]) / DSPI_D Peripheral Chip Select (PCS_D[4]) / I2C_B Serial Data Line (SDA_B) / Analog Input (AN[53])
100
3.4.7.7 PG6 - GPIO (PG[6]) / DSPI_C Peripheral Chip Select (PCS_C[1]) / Ethernet Management Data Clock (FEC_MDC) / Analog Input (AN[54])
100
3.4.7.8 PG7 - GPIO (PG[7]) / DSPI_C Peripheral Chip Select (PCS_C[2]) / Ethernet Management Data I/O (FEC_MDIO) / Analog Input (AN[55])
100
3.4.7.9 PG8 - GPIO (PG[8]) / eMIOS Channel (eMIOS[7]) / Ethernet Transmit Clock (FEC_TX_CLK) / Analog Input (AN[56])
100
3.4.7.10 PG9 - GPIO (PG[9]) / eMIOS Channel (eMIOS[6]) / Ethernet Carrier Sense (FEC_CRS) / Analog Input (AN[57])
100
3.4.7.11 PG10 - GPIO (PG[10]) / eMIOS Channel (eMIOS[5]) / Ethernet Transmit Error (FEC_TX_ER) / Analog Input (AN[58])
100
3.4.7.12 PG11 - GPIO (PG[11]) / eMIOS Channel (eMIOS[4]) / Ethernet Receive Clock (FEC_RX_CLK) / Analog Input (AN[59])
100
3.4.7.13 PG12 - GPIO (PG[12]) / eMIOS Channel (eMIOS[3]) / Ethernet Transmit Data (FEC_TXD[0]) / Analog Input (AN[60])
100
3.4.7.14 PG13 - GPIO (PG[13]) / eMIOS Channel (eMIOS[2]) / Ethernet Transmit Data (FEC_TXD[1]) / Analog Input (AN[61])
101
3.4.7.15 PG14 - GPIO (PG[14]) / eMIOS Channel (eMIOS[1] / Ethernet Transmit Data (FEC_TXD[2]) / Analog Input (AN[62])
101
3.4.7.16 PG15 - GPIO (PG[15]) / eMIOS Channel (eMIOS[0]) / Ethernet Transmit Data (FEC_TXD[3]) / Analog Input (AN[63])
101
3.4.8 Port H Pins
101
3.4.8.1 PH0 - GPIO (PH[0]) / eMIOS Channel (eMIOS[31]) / Ethernet Collision (FEC_COL)
101
3.4.8.2 PH1 - GPIO (PH[1]) / eMIOS Channel (eMIOS[30]) / Ethernet Receive Data Valid (FEC_RX_DV)
101
3.4.8.3 PH2 - GPIO (PH[2]) / eMIOS Channel (eMIOS[29]) / Ethernet Transmit Enable (FEC_TX_EN)
101
3.4.8.4 PH3 - GPIO (PH[3]) / eMIOS Channel (eMIOS[28]) / Ethernet Receive Error (FEC_RX_ER)
101
3.4.8.5 PH4 - GPIO (PH[4]) / eMIOS Channel (eMIOS[27]) / Ethernet Receive Data (FEC_RXD[0])
102
3.4.8.6 PH5 - GPIO (PH[5]) / eMIOS Channel (eMIOS[26]) / Ethernet Receive Data (FEC_RXD[1])
102
3.4.8.7 PH6 - GPIO (PH[6]) / eMIOS Channel (eMIOS[25]) / Ethernet Receive Data (FEC_RXD[2])
102
3.4.8.8 PH7 - GPIO (PH[7]) / eMIOS Channel (eMIOS[24]) / Ethernet Receive Data (FEC_RXD[3])
102
3.4.8.9 PH8 - GPIO (PH[8]) / eMIOS Channel (eMIOS[23])
102
3.4.8.10 PH9 - GPIO (PH[9]) / eMIOS Channel (eMIOS[22])
102
3.4.8.11 PH10 - GPIO (PH[10]) / eMIOS Channel (eMIOS[21])
102
3.4.8.12 PH11 - GPIO (PH[11]) / eMIOS Channel (eMIOS[20])
102
3.4.8.13 PH12 - GPIO (PH[12]) / eMIOS Channel (eMIOS[19])
102
3.4.8.14 PH13 - GPIO (PH[13]) / eMIOS Channel (eMIOS[18])
102
3.4.8.15 PH14 - GPIO (PH[14]) / eMIOS Channel (eMIOS[17])
103
3.4.8.16 PH15 - GPIO (PH[15]) / eMIOS Channel (eMIOS[16])
103
3.4.9 Port J Pins
103
3.4.9.1 PJ0 - GPIO (PJ[0]) / eMIOS Channel (eMIOS[15]) / DSPI_A Peripheral Chip Select (PCS_A[4])
103
3.4.9.2 PJ1 - GPIO (PJ[1]) / eMIOS Channel (eMIOS[14]) / DSPI_A Peripheral Chip Select (PCS_A[5])
103
3.4.9.3 PJ2 - GPIO (PJ[2]) / eMIOS Channel (eMIOS[13]) / DSPI_B Peripheral Chip Select (PCS_B[1])
103
3.4.9.4 PJ3 - GPIO (PJ[3]) / eMIOS Channel (eMIOS[12]) / DSPI_B Peripheral Chip Select (PCS_B[2])
103
3.4.9.5 PJ4 - GPIO (PJ[4]) / eMIOS Channel (eMIOS[11]) / DSPI_C Peripheral Chip Select (PCS_C[3])
103
3.4.9.6 PJ5 - GPIO (PJ[5]) / eMIOS Channel (eMIOS[10]) / DSPI_C Peripheral Chip Select (PCS_C[4])
103
3.4.9.7 PJ6 - GPIO (PJ[6]) / eMIOS Channel (eMIOS[9]) / DSPI_D Peripheral Chip Select (PCS_D[5])
104
3.4.9.8 PJ7 - GPIO (PJ[7]) / eMIOS Channel (eMIOS[8]) / DSPI_D Peripheral Chip Select (PCS_D[1])
104
3.4.9.9 PJ8 - GPIO (PJ[8]) / eMIOS Channel (eMIOS[7])
104
3.4.9.10 PJ9 - GPIO (PJ[9]) / eMIOS Channel (eMIOS[6])
104
3.4.9.11 PJ10 - GPIO (PJ[10]) / eMIOS Channel (eMIOS[5])
104
3.4.9.12 PJ11 - GPIO (PJ[11]) / eMIOS Channel (eMIOS[4])
104
3.4.9.13 PJ12 - GPIO (PJ[12]) / eMIOS Channel (eMIOS[3])
104
3.4.9.14 PJ13 - GPIO (PJ[13]) / eMIOS Channel (eMIOS[2])
104
3.4.9.15 PJ14 - GPIO (PJ[14]) / eMIOS Channel (eMIOS[1])
104
3.4.9.16 PJ15 - GPIO (PJ[15]) / eMIOS Channel (eMIOS[0])
105
3.4.10 Port K Pins
105
3.4.10.1 PK0 - GPIO (PK[0]) / Media Local Bus Clock (MLBCLK) / DSPI_B Clock (SCK_B) / Clock Output (CLKOUT)
105
3.4.10.2 PK1 - GPIO (PK[1]) / Media Local Bus Signal (MLBSIG) / DSPI_B Data Output (SOUT_B) / DSPI_D Peripheral Chip Select (PCS_D[4])
105
3.4.10.3 PK2 - GPIO (PK[2]) / Media Local Bus Data (MLBDAT) / DSPI_B Data Input (SIN_B) / DSPI_D Peripheral Chip Select (PCS_D[5])
105
3.4.10.4 PK3 - GPIO (PK[3]) / FlexRay Channel A Receive (FR_A_RX) / External Analog Mux Address Output (MA[0]) / DSPI_C Peripheral Chip Select (PCS_C[1])
105
3.4.10.5 PK4 - GPIO (PK[4]) / FlexRay Channel A Transmit (FR_A_TX) / External Analog Mux Address Output (MA[1]) / DSPI_C Peripheral Chip Select (PCS_C[2])
105
3.4.10.6 PK5 - GPIO (PK[5]) / FlexRay Channel A Transmit Enable (FR_A_TX_EN) / External Analog Mux Address Output (MA[2]) / DSPI_C Peripheral Chip Select (PCS_C[3])
106
3.4.10.7 PK6 - GPIO (PK[6]) / FlexRay Channel B Receive (FR_B_RX) / DSPI_B Peripheral Chip Select (PCS_B[1]) / DSPI_C Peripheral Chip Select (PCS_C[4])
106
3.4.10.8 PK7 - GPIO (PK[7]) / FlexRay Channel B Transmit (FR_B_TX) / DSPI_B Peripheral Chip Select (PCS_B[2]) / DSPI_C Peripheral Chip Select (PCS_C[5])
106
3.4.10.9 PK8 - GPIO (PK[8]) / FlexRay Channel B Transmit Enable (FR_B_TX_EN) / DSPI_B Peripheral Chip Select (PCS_B[3]) / DSPI_A Peripheral Chip Select (PCS_A[1])
106
3.4.10.10 PK9 - GPIO (PK[9]) / Clock Output (CLKOUT) / DSPI_D Peripheral Chip Select (PCS_D[1]) / DSPI_A Peripheral Chip Select (PCS_A[2]) / Boot Configuration (BOOTCFG)
106
3.4.10.11 PK10 - GPIO (PK[10]) / DSPI_B Peripheral Chip Select (PCS_B[5]) / DSPI_D Peripheral Chip Select (PCS_D[2]) / DSPI_A Peripheral Chip Select (PCS_A[3])
107
3.4.11 Nexus Signals
107
3.4.11.1 Nexus Event In EVTI
107
3.4.11.2 Nexus Event Out EVTO
107
3.4.11.3 Nexus Message Clock Out MCKO
107
3.4.11.4 Nexus Message Data Out MDO[0]
107
3.4.11.5 Nexus Message Data Out MDO[11:1]
107
3.4.11.6 Nexus Message Start/End Out MSEO[1:0]
108
3.4.12 Reset and Configuration Signals
108
3.4.12.1 External Reset Input RESET
108
3.4.13 JTAG Signals
108
3.4.13.1 JTAG Test Clock Input TCK
108
3.4.13.2 JTAG Test Data Input TDI
108
3.4.13.3 JTAG Test Data Output TDO
108
3.4.13.4 JTAG Test Mode Select Input TMS
108
3.4.13.5 JTAG Compliance Input JCOMP
108
3.4.13.6 Test Mode Enable Input TEST
108
3.4.14 Clock Synthesizer Signals
109
3.4.14.1 Crystal Oscillator Input / External Clock Input EXTAL
109
3.4.14.2 Crystal Oscillator Output XTAL
109
3.4.14.3 System Clock Output CLKOUT
109
3.4.15 Power / Ground Signals
109
3.4.15.1 Internal Logic Supply Input VDD
109
3.4.15.2 Fixed 3.3V Internal Supply Input VDD33
109
3.4.15.3 Analog Supply VDDA
109
3.4.15.4 External I/O Supply Input VDDEn
109
3.4.15.5 Media Local Bus Supply Input VDDEMLB
109
3.4.15.6 Nexus Interface Supply Input VDDENEX
110
3.4.15.7 Clock Synthesizer Power Input VDDSYN
110
3.4.15.8 Voltage Regulator Control Voltage VRC
110
3.4.15.9 Voltage Regulator Control Output VRCCTL
110
3.4.15.10 Supply VRCSEL
110
3.4.15.11 Analog High Voltage Reference VRH
110
3.4.15.12 Analog Low Voltage Reference VRL
110
3.4.15.13 Ground VSS
110
3.4.15.14 Analog Ground VSSA
110
3.4.15.15 Clock Synthesizer Ground Input VSSSYN
111
Chapter 4 Resets
113
4.1 Introduction
113
4.2 External Signal Description
113
4.2.1 Reset (RESET)
114
4.2.2 Boot Configuration (BOOTCFG)
114
4.3 Functional Description
114
4.3.1 Z6, Z0 Cores Reset Vectors
114
4.3.2 Reset Sources
114
4.3.2.1 Power-on Reset (POR)
114
4.3.2.2 Low-Voltage Inhibit (LVI) Resets
115
4.3.2.3 External Reset
115
4.3.2.4 Loss-of-Lock Reset
115
4.3.2.5 Loss-of-Clock Reset
115
4.3.2.6 Watchdog Timer Reset
115
4.3.2.7 Z6 Core Checkstop Reset
115
4.3.2.8 Z0 Core Checkstop Reset
116
4.3.2.9 JTAG Reset
116
4.3.2.10 Software System Reset
116
4.4 Reset Configuration
116
4.4.1 Reset Configuration Timing
117
Chapter 5 System Clock Description
119
5.1 Introduction
119
5.1.1 Features
119
5.1.2 Clock Sources
120
5.1.3 External High-Frequency Crystal (4 - 40 MHz XTAL)
121
5.1.3.1 4 - 40 MHz XTAL Features
121
5.1.4 Internal High-Frequency RC Oscillator (16 MHz_IRC)
122
5.1.4.1 16 MHz_IRC Features
122
5.1.5 Internal Low-Frequency RC Oscillator (128 kHz_IRC)
122
5.1.5.1 128 kHz_IRC Features
122
5.1.6 External Low-Frequency Crystal (32 kHz_XTAL)
123
5.1.6.1 32 kHz_XTAL Features
123
5.1.7 FMPLL
123
5.1.7.1 FMPLL Features
123
5.2 System Clock Architecture
124
5.3 Clock Dividers
126
5.3.1 System Clock Select
126
5.3.2 System Clock Dividers
126
5.3.3 External Bus Clock (CLKOUT) Divider
126
5.3.4 Nexus Message Clock (MCKO) Divider
127
5.3.5 Peripheral Clock Dividers
127
5.4 Software-Controlled Power Management
128
5.4.1 Module Disable (MDIS) Clock Gating
128
5.4.2 Halt Clock Gating
129
5.4.3 Core WAIT Clock Gating
129
5.5 Alternate Module Clock Domains
130
5.5.1 FlexCAN Clock Domains
130
5.5.2 FlexRay Clock Domains
130
5.5.3 API / RTC Clock Domains
131
5.5.4 SWT Clock Domain
132
5.5.5 Input/Output Processor (IOP) Clocking
132
5.5.6 FEC Clocking
132
5.5.7 Media Local Bus (MLB) DIM Clocking
132
Chapter 6 Clocks, Reset, and Power (CRP)
133
6.1 Introduction
133
6.1.1 Block Diagram
133
6.1.2 Features
134
6.1.3 Modes of Operation
136
6.2 Memory Map and Registers
136
6.2.1 Module Memory Map
136
6.2.2 Register Descriptions
137
6.2.2.1 Clock Source Register (CRP_CLKSRC)
137
6.2.2.2 RTC Control Register (CRP_RTCC)
138
6.2.2.3 RTC Status Register (CRP_RTSC)
140
6.2.2.4 RTC Counter Register (CRP_RTCCNT)
141
6.2.2.5 Pin Wakeup Enable Registers (CRP_PWKENH/L)
141
6.2.2.6 Pin Wakeup Source Interrupt Enable Register (CRP_PWKSRCIE)
143
6.2.2.7 Pin Wakeup Source Flag Register (CRP_PWKSRCF)
143
6.2.2.8 Z6 Reset Vector Register (CRP_Z6VEC)
144
6.2.2.9 Z0 Reset Vector Register (CRP_Z0VEC)
144
6.2.2.10 Reset Recovery Pointer Register (CRP_RECPTR)
145
6.2.2.11 Power Status and Control Register (CRP_PSCR)
146
6.2.2.12 SoC Status and Control Register (CRP_SOCSC)
147
6.3 Functional Description
149
6.3.1 Low-Power Mode
149
6.3.2 Wake-Up Lines
149
6.3.3 Low-Power Mode Entry
150
6.3.3.1 CRP Clock Selection
150
6.3.3.2 Sleep Mode RAM Retention
151
6.3.4 Low-Power Operation
151
6.3.4.1 Sleep Mode Reset Operation
155
6.3.5 Low-Power Wakeup
155
6.3.5.1 Low Power Mode Debug Support
156
6.4 Real-Time Counter (RTC)
157
6.4.1 RTC Features
158
6.4.2 RTC Functional Description
158
6.4.3 Register Description
160
6.5 Power Supply Monitors
161
6.5.1 Power-On Reset (POR)
161
6.5.2 Low-Voltage Monitors (LVI)
161
Chapter 7 Frequency Modulated Phase-Locked Loop (FMPLL)
163
7.1 Introduction
163
7.1.1 Block Diagram
163
7.1.2 Features
163
7.1.3 Modes of Operation
164
7.2 External Signal Description
164
7.3 Memory Map and Registers
164
7.3.1 Module Memory Map
164
7.3.2 Register Descriptions
165
7.3.2.1 FMPLL Synthesizer Status Register (SYNSR)
165
7.3.2.2 FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1)
167
7.3.2.3 FMPLL Enhanced Synthesizer Control Register 2 (ESYNCR2)
169
7.4 Functional Description
172
7.4.1 General
172
7.4.2 PLL Off Mode
173
7.4.3 Normal Mode
173
7.4.3.1 PLL Lock Detection
173
7.4.3.2 Loss-of-Clock Detection
174
7.4.3.3 PLL Normal Mode Without FM
175
7.4.3.4 PLL Normal Mode With Frequency Modulation
177
7.5 Resets
180
7.5.1 Clock Mode Selection
180
7.5.1.1 Power-On Reset (POR)
180
7.5.1.2 External Reset
180
7.5.2 PLL Loss-of-Lock Reset
181
7.5.3 PLL Loss-of-Clock Reset
181
7.6 Interrupts
181
7.6.1 Loss-of-Lock Interrupt Request
181
7.6.2 Loss-of-Clock Interrupt Request
181
Chapter 8 System Integration Unit (SIU)
183
8.1 Introduction
183
8.1.1 Block Diagram
183
8.1.2 Features
184
8.1.3 Modes of Operation
185
8.1.3.1 Normal Mode
185
8.1.3.2 Debug Mode
185
8.2 External Signal Description
185
8.2.1 Ports vs. General-Purpose I/O Pins
186
8.3 Memory Map and Registers
186
8.3.1 Module Memory Map
186
8.3.2 Register Descriptions
195
8.3.2.1 MCU ID Register (SIU_MIDR)
195
8.3.2.2 Reset Status Register (SIU_RSR)
196
8.3.2.3 System Reset Control Register (SIU_SRCR)
197
8.3.2.4 External Interrupt Status Register (SIU_EISR)
198
8.3.2.5 DMA/Interrupt Request Enable Register (SIU_DIRER)
199
8.3.2.6 DMA/Interrupt Request Select Register (SIU_DIRSR)
200
8.3.2.7 Overrun Status Register (SIU_OSR)
201
8.3.2.8 Overrun Request Enable Register (SIU_ORER)
201
8.3.2.9 IRQ Rising-Edge Event Enable Register (SIU_IREER)
202
8.3.2.10 IRQ Falling-Edge Event Enable Register (SIU_IFEER)
202
8.3.2.11 External IRQ Digital Filter Register (SIU_IDFR)
203
8.3.2.12 IRQ Filtered Input Register (SIU_IFIR)
204
8.3.2.13 Pad Configuration Registers (SIU_PCR)
204
8.3.2.14 GPIO Pin Data Output Registers (SIU_GPDO16_19-SIU_GPDO152_154)
208
8.3.2.15 GPIO Pin Data Input Registers (SIU_GPDI0_3-SIU_GPDI152_154)
210
8.3.2.16 IMUX Select Register 1 (SIU_ISEL1)
211
8.3.2.17 IMUX Select Register 2 (SIU_ISEL2)
215
8.3.2.18 IMUX Select Register 4 (SIU_ISEL4)
217
8.3.2.19 Chip Configuration Register (SIU_CCR)
218
8.3.2.20 External Clock Control Register (SIU_ECCR)
219
8.3.2.21 General Purpose Register 0-3 (SIU_GPRn)
220
8.3.2.22 System Clock Register (SIU_SYSCLK)
220
8.3.2.23 Halt Register (SIU_HLTn)
221
8.3.2.24 Halt Acknowledge Register (SIU_HLTACKn)
223
8.3.2.25 eMIOS Select Register n (SIU_EMIOS_SELn)
226
8.3.2.26 External Interrupt Select Register 2A (SIU_ISEL2A)
227
8.3.2.27 Parallel GPIO Pin Data Output Register 0 (SIU_PGPDO0)
230
8.3.2.28 Parallel GPIO Pin Data Output Register 1 (SIU_PGPDO1)
230
8.3.2.29 Parallel GPIO Pin Data Output Register 2 (SIU_PGPDO2)
231
8.3.2.30 Parallel GPIO Pin Data Output Register 3 (SIU_PGPDO3)
231
8.3.2.31 Parallel GPIO Pin Data Output Register 4 (SIU_PGPDO4)
231
8.3.2.32 Parallel GPIO Pin Data Input Register 0 (SIU_PGPDI0)
232
8.3.2.33 Parallel GPIO Pin Data Input Register 1 (SIU_PGPDI1)
232
8.3.2.34 Parallel GPIO Pin Data Input Register 2 (SIU_PGPDI2)
233
8.3.2.35 Parallel GPIO Pin Data Input Register 3 (SIU_PGPDI3)
233
8.3.2.36 Parallel GPIO Pin Data Input Register 4 (SIU_PGPDI4)
234
8.3.2.37 Masked Parallel GPIO Pin Data Output Register 1 (SIU_MPGPDO1)
234
8.3.2.38 Masked Parallel GPIO Pin Data Output Register 2 (SIU_MPGPDO2)
235
8.3.2.39 Masked Parallel GPIO Pin Data Output Register 3 (SIU_MPGPDO3)
235
8.3.2.40 Masked Parallel GPIO Pin Data Output Register 4 (SIU_MPGPDO4)
236
8.3.2.41 Masked Parallel GPIO Pin Data Output Register 5 (SIU_MPGPDO5)
236
8.3.2.42 Masked Parallel GPIO Pin Data Output Register 6 (SIU_MPGPDO6)
237
8.3.2.43 Masked Parallel GPIO Pin Data Output Register 7 (SIU_MPGPDO7)
237
8.3.2.44 Masked Parallel GPIO Pin Data Output Register 8 (SIU_MPGPDO8)
238
8.3.2.45 Masked Parallel GPIO Pin Data Output Register 9 (SIU_MPGPDO9)
238
8.3.2.46 Masked Serial GPO Register for DSPI_A High (SIU_DSPIAH)
239
8.3.2.47 Masked Serial GPO Register for DSPI_A Low (SIU_DSPIAL)
240
8.3.2.48 Masked Serial GPO Register for DSPI_B High (SIU_DSPIBH)
240
8.3.2.49 Masked Serial GPO Register for DSPI_B Low (SIU_DSPIBL)
241
8.3.2.50 Masked Serial GPO Register for DSPI_C High (SIU_DSPICH)
242
8.3.2.51 Masked Serial GPO Register for DSPI_C Low (SIU_DSPICL)
242
8.3.2.52 Masked Serial GPO Register for DSPI_D High (SIU_DSPIDH)
243
8.3.2.53 Masked Serial GPO Register for DSPI_D Low (SIU_DSPIDL)
244
8.3.2.54 eMIOS Select Register for DSPI_A (SIU_EMIOSA)
244
8.3.2.55 SIU_DSPIAH/L Select Register for DSPI_A (SIU_DSPIAHLA)
245
8.3.2.56 eMIOS Select Register for DSPI_B (SIU_EMIOSB)
246
8.3.2.57 SIU_DSPIBH/L Select Register for DSPI_B (SIU_DSPIAHLB)
246
8.3.2.58 eMIOS Select Register for DSPI_C (SIU_EMIOSC)
247
8.3.2.59 SIU_DSPICH/L Select Register for DSPI_C (SIU_DSPICHLC)
247
8.3.2.60 eMIOS Select Register for DSPI_D (SIU_EMIOSD)
248
8.3.2.61 SIU_DSPIDH/L Select Register for DSPI_D (SIU_DSPIDHLD)
249
8.4 Functional Description
250
8.4.1 System Configuration
250
8.4.1.1 Boot Configuration
250
8.4.1.2 Pad Configuration
250
8.4.2 Reset Control
250
8.4.3 External Interrupt
250
8.4.4 GPIO Operation
251
8.4.5 Internal Multiplexing
251
8.4.5.1 ADC External Trigger Input Multiplexing
251
8.4.5.2 SIU External Interrupt Input Multiplexing
252
8.4.5.3 SIU EMIOS/DSPI Multiplexing
253
Chapter 9 Boot Assist Module (BAM)
255
9.1 Introduction
255
9.1.1 Features
255
9.1.2 Modes of Operation
256
9.1.2.1 Normal Mode
256
9.1.2.2 Debug Mode
256
9.1.2.3 Internal-Boot Mode
256
9.1.2.4 Serial-Boot Mode
256
9.2 Memory Map and Registers
256
9.2.1 Module Memory Map
256
9.2.2 Register Descriptions
257
9.3 Functional Description
257
9.3.1 BAM Program Resources
257
9.3.2 BAM Program Operation
257
9.3.3 Features
259
9.3.3.1 Internal-Boot Mode
260
9.3.3.2 Serial-Boot Mode Features
262
Chapter 10 Interrupts and Interrupt Controller (INTC)
269
10.1 Introduction
269
10.1.1 Block Diagram
269
10.1.2 Interrupt Controller Features
271
10.1.3 Modes of Operation
271
10.1.3.1 Software Vector Mode
271
10.1.3.2 Hardware Vector Mode
274
10.2 External Signal Description
275
10.3 Memory Map and Registers
276
10.3.1 INTC Memory Map
276
10.3.2 Register Descriptions
277
10.3.2.1 INTC Module Configuration Register (INTC_MCR)
277
10.3.2.2 INTC Current Priority Register for Processor 0 (Z6) (INTC_CPR_PRC0)
278
10.3.2.3 INTC Current Priority Register for Processor 1 (Z0) (INTC_CPR_PRC1)
280
10.3.2.4 INTC Interrupt Acknowledge Register for Processor 0 (Z6) (INTC_IACKR_PRC0)
280
10.3.2.5 INTC Interrupt Acknowledge Register for Processor 1 (Z0) (INTC_IACKR_PRC1)
282
10.3.2.6 INTC End-of-Interrupt Register for Processor 0 (Z6) (INTC_EOIR_PRC0)
282
10.3.2.7 INTC End-of-Interrupt Register for Processor 1 (Z0) (INTC_EOIR_PRC1)
283
10.3.2.8 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3-INTC_SSCIR4_7)
283
10.3.2.9 INTC Priority Select Registers (INTC_PSR0_3-INTC_PSR312_315)
284
10.4 Functional Description
287
10.4.1 External Interrupt Request Sources
287
10.4.1.1 Peripheral Interrupt Requests
301
10.4.1.2 Software Settable Interrupt Requests
301
10.4.1.3 Unique Vector for Each Interrupt Request Source
302
10.4.2 Priority Management
302
10.4.2.1 Current Priority and Preemption
302
10.4.2.2 Last-In First-Out (LIFO)
303
10.4.3 Details on Handshaking with Processor
304
10.4.3.1 Software Vector Mode Handshaking
304
10.4.3.2 Hardware Vector Mode Handshaking
305
10.5 Initialization/Application Information
306
10.5.1 Initialization Flow
306
10.5.2 Interrupt Exception Handler
306
10.5.2.1 Software Vector Mode
307
10.5.2.2 Hardware Vector Mode
307
10.5.3 ISR, RTOS, and Task Hierarchy
308
10.5.4 Order of Execution
309
10.5.5 Priority Ceiling Protocol
310
10.5.5.1 Elevating Priority
310
10.5.5.2 Ensuring Coherency
310
10.5.6 Selecting Priorities According to Request Rates and Deadlines
312
10.5.7 Software Settable Interrupt Requests
312
10.5.7.1 Scheduling a Lower Priority Portion of an ISR
312
10.5.7.2 Scheduling an ISR on Another Processor
313
10.5.8 Lowering Priority Within an ISR
313
10.5.9 Negating an Interrupt Request Outside of its ISR
314
10.5.9.1 Negating an Interrupt Request as a Side Effect of an ISR
314
10.5.9.2 Negating Multiple Interrupt Requests in One ISR
314
10.5.9.3 Proper Setting of Interrupt Request Priority
314
10.5.10 Examining LIFO Contents
314
10.6 Non-Maskable Interrupt (NMI)
315
10.7 Dynamic Interrupt Priority Elevation
316
10.7.1 e200z6 Dynamic Priority Elevation
316
10.7.2 e200z0 Dynamic Priority Elevation
316
10.7.3 eDMA Dynamic Interrupt Priority Elevation
317
Chapter 11 General-Purpose Static RAM (SRAM)
319
11.1 Introduction
319
11.1.1 Block Diagram
319
11.1.2 Features
320
11.1.3 Modes of Operation
321
11.1.3.1 Normal (Functional) Mode
321
11.1.3.2 Sleep Mode
321
11.2 External Signal Description
321
11.3 Memory Map and Registers
321
11.4 Functional Description
321
11.5 SRAM ECC Mechanism
321
11.5.1 Access Timing
322
11.5.2 Reset Operation
323
11.6 DMA Requests
324
11.7 Interrupt Requests
324
11.8 Initialization and Application Information
324
11.8.1 Example Code
324
Chapter 12 Flash Memory Array and Control
327
12.1 Introduction
327
12.1.1 Block Diagram
328
12.1.2 Features
329
12.1.3 Modes of Operation
329
12.1.3.1 Flash User Mode
329
12.1.3.2 Sleep Mode
329
12.1.3.3 User Test Mode (UTest)
330
12.2 External Signal Description
330
12.3 Memory Map and Registers
330
12.3.1 Module Memory Map
330
12.3.2 Register Descriptions
332
12.3.2.1 Module Configuration Register (MCR)
332
12.3.2.2 Low/Mid Address Space Block Locking Register (LML)
336
12.3.2.3 High Address Space Block Locking Register (HBL)
338
12.3.2.4 Secondary Low/Mid Address Space Block Locking Register (SLL)
339
12.3.2.5 Low/Mid Address Space Block Select Register (LMS)
340
12.3.2.6 High Address Space Block Select Register (HBS)
341
12.3.2.7 Address Register (ADR)
342
12.3.2.8 Platform Flash Configuration Register for Port n (PFCRPn)
343
12.3.2.9 Platform Flash Access Protection Register (PFAPR)
346
12.3.2.10 PFlash Supervisor Access Control Register (PFSACC)
347
12.3.2.11 PFlash Data Access Control Register (PFDACC)
349
12.3.2.12 User Test Register 0 (UT0)
349
12.3.2.13 User Test Register 1 (UT1)
351
12.3.2.14 User Test Register 2 (UT2)
352
12.3.2.15 User Multiple Input Signature Register [0:4] (UMn)
352
12.4 Functional Description
353
12.4.1 Flash User Mode
353
12.4.1.1 Flash Read and Write
353
12.4.1.2 Read While Write (RWW)
354
12.4.1.3 Flash Programming
354
12.4.1.4 Flash Erase
358
12.4.1.5 Flash Erase Suspend/Resume
359
12.4.2 UTest Mode
361
12.4.2.1 Array Integrity Self Check
361
12.4.2.2 Factory Margin Read
362
12.4.2.3 ECC Logic Check
363
12.4.3 Flash Shadow Block
363
12.4.4 Flash Sleep Mode
364
12.4.5 Flash Reset
364
12.4.6 DMA Requests
364
12.4.7 Interrupt Requests
364
Chapter 13 e200z6 Core (Z6)
365
13.1 Introduction
365
13.1.1 Block Diagram
365
13.1.2 Overview
366
13.1.3 Features
367
13.1.3.1 Instruction Unit Features
368
13.1.3.2 Integer Unit Features
368
13.1.3.3 Load/Store Unit Features
368
13.1.3.4 MMU Features
368
13.1.3.5 L1 Cache Features
369
13.1.3.6 BIU Features
369
13.1.4 Microarchitecture Summary
369
13.2 Core Registers and Programmer’s Model
370
13.2.1 Power Architecture Registers
374
13.2.1.1 User-Level Registers
374
13.2.1.2 Supervisor-Level Only Registers
374
13.2.2 Core-Specific Registers
376
13.2.2.1 User-Level Registers
376
13.2.2.2 Supervisor-Level Registers
377
13.2.3 e200z6 Core Complex Features Not Supported in the Device
378
13.3 Functional Description
378
13.3.1 Memory Management Unit (MMU)
378
13.3.1.1 Translation Lookaside Buffer (TLB)
379
13.3.1.2 Translation Flow
379
13.3.1.3 Effective to Real Address Translation
380
13.3.1.4 Permissions
380
13.3.1.5 MMU Assist Registers (MAS[0:4], MAS[6])
381
13.3.2 L1 Cache
385
13.3.2.1 Cache Organization
386
13.3.2.2 Cache Lookup
387
13.3.2.3 Cache Line Replacement Algorithm
389
13.3.2.4 Cache Power Reduction
389
13.3.2.5 L1 Cache Control and Status Register 0 (L1CSR0)
389
13.3.2.6 L1 Cache Configuration Register 0 (L1CFG0)
392
13.3.3 Interrupt Types
393
13.3.4 Bus Interface Unit (BIU)
395
13.3.5 Timer Facilities
395
13.3.6 Signal Processing Extension APU (SPE APU)
396
13.3.6.1 Overview
396
13.3.7 SPE Programming Model
396
13.3.8 12.3.8 Wait Instruction
397
13.4 Power Architecture Instruction Extensions - VLE
397
13.5 External References
398
Chapter 14 e200z0 Core (Z0)
399
14.1 Introduction
399
14.1.1 Features
399
14.2 Microarchitecture Summary
400
14.2.1 Instruction Unit Features
401
14.2.2 Integer Unit Features
402
14.2.3 Load/Store Unit Features
402
14.2.4 e200z0 System Bus Features
402
14.2.5 Nexus 2+ Features
402
14.3 Core Registers and Programmer’s Model
403
14.3.1 Power Architecture Book E Registers
405
14.3.1.1 User-Level Registers
405
14.3.1.2 Supervisor-Level Registers
406
14.3.2 e200-Specific Special Purpose Registers
407
14.3.2.1 User-Level Registers
407
14.3.2.2 Supervisor-Level Registers
408
14.3.3 e200z0 Core Complex Features not Supported on the PXN20
409
14.4 Interrupt Types
409
14.5 Bus Interface Unit (BIU)
411
Chapter 15 Semaphores
413
15.1 Introduction
413
15.1.1 Block Diagram
413
15.1.2 Features
414
15.1.3 Modes of Operation
415
15.2 Signal Description
415
15.3 Memory Map and Registers
415
15.3.1 Module Memory Map
415
15.3.2 Register Descriptions
416
15.3.2.1 Semaphores Gate n Register (SEMA4_GATEn)
416
15.3.2.2 Semaphores Processor n IRQ Notification Enable (SEMA4_CP{0,1}INE)
417
15.3.2.3 Semaphores Processor n IRQ Notification (SEMA4_CP{0,1}NTF)
418
15.3.2.4 Semaphores (Secure) Reset Gate n (SEMA4_RSTGT)
418
15.3.2.5 Semaphores (Secure) Reset IRQ Notification (SEMA4_RSTNTF)
420
15.4 Functional Description
422
15.4.1 Semaphore Usage
424
15.5 Initialization Information
424
15.6 Application Information
424
15.7 DMA Requests
426
15.8 Interrupt Requests
426
Chapter 16 AMBA Crossbar Switch (AXBS)
427
16.1 Introduction
427
16.1.1 Block Diagram
427
16.1.2 AXBS Controller Configuration
427
16.1.3 Overview
428
16.1.4 Features
428
16.1.5 Modes of Operation
429
16.1.5.1 Normal Mode
429
16.1.5.2 Debug Mode
429
16.2 Memory Map and Register Definition
429
16.2.1 Register Descriptions
430
16.2.1.1 Master Priority Registers (XBAR_MPRn)
430
16.2.1.2 Slave General-Purpose Control Registers (XBAR_SGPCRn)
432
16.2.1.3 Master General Purpose Control Registers (XBAR_MGPCRn)
434
16.3 Functional Description
434
16.3.1 Overview
434
16.3.2 General Operation
435
16.3.3 Master Ports
435
16.3.4 Slave Ports
436
16.3.5 Priority Assignment
436
16.3.6 Arbitration
436
16.3.6.1 Fixed Priority Operation
436
16.3.6.2 Round-Robin Priority Operation
437
Chapter 17 Peripheral Bridge (AIPS-lite)
439
17.1 Introduction
439
17.1.1 Block Diagram
439
17.1.2 Features
439
17.1.3 Modes of Operation
440
17.2 External Signal Description
440
17.3 Memory Map and Register Description
440
17.4 Functional Description
440
17.4.1 Read Cycles
440
17.4.2 Write Cycles
440
Chapter 18 Memory Protection Unit (MPU)
441
18.1 Introduction
441
18.1.1 Block Diagram
441
18.1.2 Features
442
18.1.3 Modes of Operation
443
18.2 Signal Description
443
18.3 Memory Map and Registers
443
18.3.1 Module Memory Map
443
18.3.2 Register Descriptions
445
18.3.2.1 MPU Control/Error Status Register (MPU_CESR)
445
18.3.2.2 MPU Error Address Register, MPU Port 0 to 3 (MPU_EARn)
446
18.3.2.3 MPU Error Detail Register, MPU Port 0 to 3 (MPU_EDRn)
447
18.3.2.4 MPU Region Descriptor n (MPU_RGDn)
448
18.3.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
453
18.4 Functional Description
455
18.4.1 Access Evaluation Macro
455
18.4.1.1 Access Evaluation-Hit Determination
456
18.4.1.2 Access Evaluation-Privilege Violation Determination
456
18.4.2 Putting It All Together and AHB Error Terminations
457
18.5 Initialization Information
457
18.6 Application Information
458
Chapter 19 Error Correction Status Module (ECSM)
461
19.1 Introduction
461
19.1.1 Features
461
19.2 Memory Map and Registers
461
19.2.1 Module Memory Map
462
19.2.2 Register Descriptions
463
19.2.2.1 FEC Burst Optimization Master Control Register (FBOMCR)
463
19.2.2.2 ECC Configuration Register (ECR)
465
19.2.2.3 ECC Status Register (ESR)
466
19.2.2.4 ECC Error Generation Register (EEGR)
467
19.2.2.5 Platform Flash ECC Address Register (PFEAR)
469
19.2.2.6 Platform Flash ECC Master Number Register (PFEMR)
470
19.2.2.7 Platform Flash ECC Attributes Register (PFEAT)
470
19.2.2.8 Platform Flash ECC Data Register (PFEDR)
471
19.2.2.9 Platform RAM ECC Address Register (PREAR)
472
19.2.2.10 Platform RAM ECC Syndrome Register (PRESR)
473
19.2.2.11 Platform RAM ECC Master Number Register (PREMR)
474
19.2.2.12 Platform RAM ECC Attributes Register (PREAT)
475
19.2.2.13 Platform RAM ECC Data Register (PREDR)
476
Chapter 20 Software Watchdog Timer (SWT)
479
20.1 Introduction
479
20.1.1 Features
479
20.1.2 Modes of Operation
479
20.2 External Signal Description
479
20.3 Memory Map and Register Definition
480
20.3.1 Memory Map
480
20.3.2 Register Descriptions
480
20.3.2.1 SWT Control Register (SWT_CR)
480
20.3.2.2 SWT Interrupt Register (SWT_IR)
482
20.3.2.3 SWT Time-Out Register (SWT_TO)
482
20.3.2.4 SWT Window Register (SWT_WN)
483
20.3.2.5 SWT Service Register (SWT_SR)
484
20.3.2.6 SWT Counter Output Register (SWT_CO)
484
20.3.2.7 SWT Service Key Register (SWT_SK)
485
20.4 Functional Description
485
Chapter 21 System Timer Module (STM)
489
21.1 Overview
489
21.1.1 Features
489
21.1.2 Modes of Operation
489
21.1.3 Clocking
489
21.1.4 Interrupts
489
21.2 External Signal Description
489
21.3 Memory Map and Register Definition
490
21.3.1 Memory Map
490
21.3.2 Register Descriptions
490
21.3.2.1 STM Control Register (STM_CR)
491
21.3.2.2 STM Count Register (STM_CNT)
491
21.3.2.3 STM Channel Control Register (STM_CCRn)
492
21.3.2.4 STM Channel Interrupt Register (STM_CIRn)
492
21.3.2.5 STM Channel Compare Register (STM_CMPn)
493
21.4 Functional Description
493
Chapter 22 Periodic Interrupt Timer (PIT)
495
22.1 Introduction
495
22.1.1 Block Diagram
495
22.1.2 Features
496
22.1.3 Modes of Operation
496
22.2 Signal Description
496
22.2.1 External Signal Description
496
22.3 Memory Map and Registers
496
22.3.1 Module Memory Map
496
22.3.2 Register Descriptions
498
22.3.2.1 PIT Module Control Register (PITMCR)
498
22.3.2.2 Timer n Load Value Register (LDVALn)
499
22.3.2.3 Timer n Current Value Register (CVALn)
499
22.3.2.4 Timer n Control Register (TCTRLn)
500
22.3.2.5 Timer n Flag Register (TFLGn)
501
22.4 Functional Description
502
22.4.1 Timers
502
22.4.2 Debug Mode
503
22.4.3 Interrupts
503
22.5 Initialization and Application Information
503
22.5.1 Example Configuration
503
Chapter 23 DMA Channel Multiplexer (DMA_MUX)
505
23.1 Introduction
505
23.1.1 Block Diagram
505
23.1.2 Features
506
23.1.3 Modes of Operation
506
23.2 External Signal Description
506
23.3 Memory Map and Registers
506
23.3.1 Module Memory Map
506
23.3.2 Register Descriptions
508
23.3.2.1 Channel Configuration Registers (CHCONFIGx)
508
23.4 Functional Description
512
23.4.1 DMA Channels 0-7
512
23.4.2 DMA Channels 8-31
514
23.4.3 Always Enabled DMA Sources
515
23.5 Initialization/Application Information
516
23.5.1 Reset
516
23.5.2 Enabling and Configuring Sources
516
23.5.2.1 Enabling a Source with Periodic Triggering
516
23.5.2.2 Enabling a Source without Periodic Triggering
517
23.5.2.3 Disabling a Source
519
23.5.2.4 Switching the Source of a DMA Channel
519
23.6 Interrupts
520
Chapter 24 Enhanced Direct Memory Access Controller (eDMA)
521
24.1 Introduction
521
24.1.1 Block Diagram
521
24.1.2 Features
522
24.1.3 Modes of Operation
522
24.1.3.1 Normal Mode
522
24.1.3.2 Debug Mode
523
24.2 External Signal Description
523
24.3 Memory Map and Registers
523
24.3.1 Module Memory Map
523
24.3.2 Register Descriptions
527
24.3.2.1 eDMA Control Register (EDMA_CR)
528
24.3.2.2 eDMA Error Status Register (EDMA_ESR)
530
24.3.2.3 eDMA Enable Request Register (EDMA_ERQRL)
532
24.3.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL)
533
24.3.2.5 eDMA Set Enable Request Register (EDMA_SERQR)
534
24.3.2.6 eDMA Clear Enable Request Register (EDMA_CERQR)
535
24.3.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
535
24.3.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
536
24.3.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR)
537
24.3.2.10 eDMA Clear Error Register (EDMA_CER)
538
24.3.2.11 eDMA Set START Bit Register (EDMA_SSBR)
538
24.3.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
539
24.3.2.13 eDMA Interrupt Request Register (EDMA_IRQRL)
539
24.3.2.14 eDMA Error Register (EDMA_ERL)
540
24.3.2.15 DMA Hardware Request Status (EDMA_HRSL)
541
24.3.2.16 eDMA Channel n Priority Registers (EDMA_CPRn)
542
24.3.2.17 Transfer Control Descriptor (TCD)
543
24.4 Functional Description
549
24.4.1 eDMA Basic Data Flow
551
24.5 Initialization / Application Information
554
24.5.1 eDMA Initialization
554
24.5.2 DMA Programming Errors
556
24.5.3 DMA Request Assignments
557
24.5.4 DMA Arbitration Mode Considerations
558
24.5.4.1 Fixed-Group Arbitration, Fixed-Channel Arbitration
558
24.5.4.2 Round-Robin Group Arbitration, Fixed-Channel Arbitration
559
24.5.4.3 Round-Robin Group Arbitration, Round-Robin Channel Arbitration
559
24.5.4.4 Fixed-Group Arbitration, Round-Robin Channel Arbitration
559
24.5.5 DMA Transfer
560
24.5.5.1 Single Request
560
24.5.5.2 Multiple Requests
561
24.5.5.3 Modulo Feature
562
24.5.6 TCD Status
563
24.5.6.1 Minor Loop Complete
563
24.5.6.2 Active Channel TCD Reads
564
24.5.6.3 Preemption Status
564
24.5.7 Channel Linking
564
24.5.8 Dynamic Programming
565
24.5.8.1 Dynamic Channel Linking and Dynamic Scatter-Gather Operation
565
Chapter 25 Fast Ethernet Controller (FEC)
567
25.1 Introduction
567
25.1.1 Block Diagram
567
25.1.2 Overview
568
25.1.3 Features
570
25.2 Modes of Operation
570
25.2.1 Full and Half Duplex Operation
570
25.2.2 Interface Options
571
25.2.2.1 10 Mbps and 100 Mbps MII Interface
571
25.2.2.2 10 Mbps 7-Wire Interface Operation
571
25.2.3 Address Recognition Options
571
25.2.4 Internal Loopback
571
25.3 Programming Model
571
25.3.1 Top Level Module Memory Map
572
25.3.2 Detailed Memory Map (Control/Status Registers)
572
25.3.3 MIB Block Counters Memory Map
574
25.3.4 Registers
576
25.3.4.1 FEC Burst Optimization Master Control Register (FBOMCR)
576
25.3.4.2 Ethernet Interrupt Event Register (EIR)
576
25.3.4.3 Ethernet Interrupt Mask Register (EIMR)
578
25.3.4.4 Receive Descriptor Active Register (RDAR)
578
25.3.4.5 Transmit Descriptor Active Register (TDAR)
579
25.3.4.6 Ethernet Control Register (ECR)
580
25.3.4.7 MII Management Frame Register (MMFR)
581
25.3.4.8 MII Speed Control Register (MSCR)
582
25.3.4.9 MIB Control Register (MIBC)
584
25.3.4.10 Receive Control Register (RCR)
584
25.3.4.11 Transmit Control Register (TCR)
586
25.3.4.12 Physical Address Low Register (PALR)
587
25.3.4.13 Physical Address Upper Register (PAUR)
587
25.3.4.14 Opcode/Pause Duration Register (OPD)
588
25.3.4.15 Descriptor Individual Upper Address Register (IAUR)
589
25.3.4.16 Descriptor Individual Lower Address (IALR)
589
25.3.4.17 Descriptor Group Upper Address (GAUR)
590
25.3.4.18 Descriptor Group Lower Address (GALR)
591
25.3.4.19 FIFO Transmit FIFO Watermark Register (TFWR)
591
25.3.4.20 FIFO Receive Bound Register (FRBR)
592
25.3.4.21 FIFO Receive Start Register (FRSR)
593
25.3.4.22 Receive Descriptor Ring Start (ERDSR)
593
25.3.4.23 Transmit Buffer Descriptor Ring Start Register (ETDSR)
594
25.3.4.24 Receive Buffer Size Register (EMRBR)
595
25.4 Functional Description
595
25.4.1 Initialization Sequence
596
25.4.1.1 Hardware Controlled Initialization
596
25.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])
596
25.4.3 Microcontroller Initialization
597
25.4.4 User Initialization (After Asserting ECR[ETHER_EN])
597
25.4.5 Network Interface Options
597
25.4.6 FEC Frame Transmission
598
25.4.7 FEC Frame Reception
600
25.4.8 Ethernet Address Recognition
601
25.4.9 Hash Algorithm
603
25.4.10 Full Duplex Flow Control
606
25.4.11 Inter-Packet Gap (IPG) Time
607
25.4.12 Collision Handling
607
25.4.13 Internal and External Loopback
607
25.4.14 Ethernet Error-Handling Procedure
608
25.4.14.1 Transmission Errors
608
25.4.14.2 Reception Errors
609
25.5 Buffer Descriptors
609
25.5.1 Driver/DMA Operation with Buffer Descriptors
609
25.5.1.1 Driver/DMA Operation with Transmit BDs
610
25.5.1.2 Driver/DMA Operation with Receive BDs
610
25.5.2 Ethernet Receive Buffer Descriptor (RxBD)
611
25.5.3 Ethernet Transmit Buffer Descriptor (TxBD)
613
Chapter 26 FlexRay Communication Controller (FlexRAY)
615
26.1 Introduction
615
26.1.1 Reference
615
26.1.2 Glossary
615
26.1.3 Color Coding
616
26.1.4 Overview
616
26.1.5 Features
618
26.1.6 Modes of Operation
619
26.1.6.1 Disabled Mode
619
26.1.6.2 Normal Mode
619
26.2 External Signal Description
620
26.2.1 Detailed Signal Descriptions
620
26.2.1.1 FR_A_RX - Receive Data Channel A
620
26.2.1.2 FR_A_TX - Transmit Data Channel A
620
26.2.1.3 FR_A_TX_EN - Transmit Enable Channel A
621
26.2.1.4 FR_B_RX - Receive Data Channel B
621
26.2.1.5 FR_B_TX - Transmit Data Channel B
621
26.2.1.6 FR_B_TX_EN - Transmit Enable Channel B
621
26.2.1.7 FR_DBG[3], FR_DBG[2], FR_DBG[1] - , FR_DBG[0] - Strobe Signals
621
26.3 Controller Host Interface Clocking
621
26.4 Protocol Engine Clocking
622
26.4.1 Oscillator Clocking
622
26.4.2 PLL Clocking
622
26.5 Memory Map and Register Description
622
26.5.1 Memory Map
622
26.5.2 Register Descriptions
625
26.5.2.1 Register Reset
626
26.5.2.2 Register Write Access
626
26.5.2.3 Module Version Register (MVR)
627
26.5.2.4 Module Configuration Register (MCR)
628
26.5.2.5 System Memory Base Address Register (SYMBADR)
629
26.5.2.6 Strobe Signal Control Register (STBSCR)
630
26.5.2.7 Message Buffer Data Size Register (MBDSR)
632
26.5.2.8 Message Buffer Segment Size and Utilization Register (MBSSUTR)
632
26.5.2.9 Protocol Operation Control Register (POCR)
633
26.5.2.10 Global Interrupt Flag and Enable Register (GIFER)
634
26.5.2.11 Protocol Interrupt Flag Register 0 (PIFR0)
637
26.5.2.12 Protocol Interrupt Flag Register 1 (PIFR1)
639
26.5.2.13 Protocol Interrupt Enable Register 0 (PIER0)
640
26.5.2.14 Protocol Interrupt Enable Register 1 (PIER1)
641
26.5.2.15 CHI Error Flag Register (CHIERFR)
642
26.5.2.16 Message Buffer Interrupt Vector Register (MBIVEC)
644
26.5.2.17 Channel A Status Error Counter Register (CASERCR)
645
26.5.2.18 Channel B Status Error Counter Register (CBSERCR)
645
26.5.2.19 Protocol Status Register 0 (PSR0)
646
26.5.2.20 Protocol Status Register 1 (PSR1)
647
26.5.2.21 Protocol Status Register 2 (PSR2)
648
26.5.2.22 Protocol Status Register 3 (PSR3)
650
26.5.2.23 Macrotick Counter Register (MTCTR)
651
26.5.2.24 Cycle Counter Register (CYCTR)
652
26.5.2.25 Slot Counter Channel A Register (SLTCTAR)
652
26.5.2.26 Slot Counter Channel B Register (SLTCTBR)
653
26.5.2.27 Rate Correction Value Register (RTCORVR)
653
26.5.2.28 Offset Correction Value Register (OFCORVR)
654
26.5.2.29 Combined Interrupt Flag Register (CIFRR)
654
26.5.2.30 System Memory Access Time-Out Register (SYMATOR)
655
26.5.2.31 Sync Frame Counter Register (SFCNTR)
656
26.5.2.32 Sync Frame Table Offset Register (SFTOR)
656
26.5.2.33 Sync Frame Table Configuration, Control, Status Register (SFTCCSR)
657
26.5.2.34 Sync Frame ID Rejection Filter Register (SFIDRFR)
658
26.5.2.35 Sync Frame ID Acceptance Filter Value Register (SFIDAFVR)
659
26.5.2.36 Sync Frame ID Acceptance Filter Mask Register (SFIDAFMR)
659
26.5.2.37 Network Management Vector Registers (NMVR0-NMVR5)
659
26.5.2.38 Network Management Vector Length Register (NMVLR)
660
26.5.2.39 Timer Configuration and Control Register (TICCR)
661
26.5.2.40 Timer 1 Cycle Set Register (TI1CYSR)
662
26.5.2.41 Timer 1 Macrotick Offset Register (TI1MTOR)
662
26.5.2.42 Timer 2 Configuration Register 0 (TI2CR0)
663
26.5.2.43 Timer 2 Configuration Register 1 (TI2CR1)
663
26.5.2.44 Slot Status Selection Register (SSSR)
664
26.5.2.45 Slot Status Counter Condition Register (SSCCR)
665
26.5.2.46 Slot Status Registers (SSR0-SSR7)
667
26.5.2.47 Slot Status Counter Registers (SSCR0-SSCR3)
668
26.5.2.48 MTS A Configuration Register (MTSACFR)
669
26.5.2.49 MTS B Configuration Register (MTSBCFR)
669
26.5.2.50 Receive Shadow Buffer Index Register (RSBIR)
670
26.5.2.51 Receive FIFO System Memory Base Address Register (RFSYMBADR)
670
26.5.2.52 Receive FIFO Periodic Timer Register (RFPTR)
671
26.5.2.53 Receive FIFO Watermark and Selection Register (RFWMSR)
672
26.5.2.54 Receive FIFO Start Index Register (RFSIR)
672
26.5.2.55 Receive FIFO Depth and Size Register (RFDSR)
673
26.5.2.56 Receive FIFO A Read Index Register (RFARIR)
673
26.5.2.57 Receive FIFO B Read Index Register (RFBRIR)
674
26.5.2.58 Receive FIFO Fill Level and POP Count Register (RFFLPCR)
674
26.5.2.59 Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
675
26.5.2.60 Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
675
26.5.2.61 Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
676
26.5.2.62 Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
676
26.5.2.63 Receive FIFO Range Filter Configuration Register (RFRFCFR)
676
26.5.2.64 Receive FIFO Range Filter Control Register (RFRFCTR)
677
26.5.2.65 Last Dynamic Transmit Slot Channel A Register (LDTXSLAR)
678
26.5.2.66 Last Dynamic Transmit Slot Channel B Register (LDTXSLBR)
678
26.5.2.67 Protocol Configuration Registers
679
26.5.2.68 Message Buffer Configuration, Control, Status Registers (MBCCSRn)
687
26.5.2.69 Message Buffer Cycle Counter Filter Registers (MBCCFRn)
689
26.5.2.70 Message Buffer Frame ID Registers (MBFIDRn)
690
26.5.2.71 Message Buffer Index Registers (MBIDXRn)
690
26.6 Functional Description
692
26.6.1 Message Buffer Concept
692
26.6.2 Physical Message Buffer
692
26.6.2.1 Message Buffer Header Field
692
26.6.2.2 Message Buffer Data Field
693
26.6.3 Message Buffer Types
693
26.6.3.1 Individual Message Buffers
693
26.6.3.2 Receive Shadow Buffers
695
26.6.3.3 Receive FIFO
695
26.6.3.4 Message Buffer Configuration and Control Data
697
26.6.3.5 Individual Message Buffer Control Data
698
26.6.3.6 Receive Shadow Buffer Configuration Data
698
26.6.3.7 Receive FIFO Control and Configuration Data
698
26.6.4 FlexRay Memory Layout
699
26.6.4.1 FlexRay Memory Layout (MCR[FAM] = 0)
699
26.6.4.2 FlexRay Memory Layout (MCR[FAM] = 1)
700
26.6.4.3 Message Buffer Header Area (MCR[FAM] = 0)
701
26.6.4.4 Message Buffer Header Area (MCR[FAM] = 1)
702
26.6.4.5 FIFO Message Buffer Header Area (MCR[FAM] = 1)
702
26.6.4.6 Message Buffer Data Area
702
26.6.4.7 Sync Frame Table Area
702
26.6.5 Physical Message Buffer Description
702
26.6.5.1 Message Buffer Protection and Data Consistency
702
26.6.5.2 Message Buffer Header Field Description
703
26.6.5.3 Message Buffer Data Field Description
710
26.6.6 Individual Message Buffer Functional Description
711
26.6.6.1 Individual Message Buffer Configuration
712
26.6.6.2 Single Transmit Message Buffers
713
26.6.6.3 Receive Message Buffers
721
26.6.6.4 Double Transmit Message Buffer
728
26.6.7 Individual Message Buffer Search
736
26.6.7.1 Message Buffer Cycle Counter Filtering
738
26.6.7.2 Message Buffer Channel Assignment Consistency
738
26.6.7.3 Node Related Slot Multiplexing
738
26.6.7.4 Message Buffer Search Error
739
26.6.8 Individual Message Buffer Reconfiguration
739
26.6.8.1 Reconfiguration Schemes
739
26.6.9 Receive FIFOs
740
26.6.9.1 Overview
740
26.6.9.2 FIFO Configuration
740
26.6.9.3 FIFO Periodic Timer
741
26.6.9.4 FIFO Reception
741
26.6.9.5 FIFO Almost-Full Interrupt Generation
742
26.6.9.6 FIFO Overflow Error Generation
742
26.6.9.7 FIFO Message Access
742
26.6.9.8 FIFO Update
742
26.6.9.9 FIFO Filtering
743
26.6.10 Channel Device Modes
746
26.6.10.1 Dual Channel Device Mode
746
26.6.10.2 Single Channel Device Mode
747
26.6.11 External Clock Synchronization
748
26.6.12 Sync Frame ID and Sync Frame Deviation Tables
749
26.6.12.1 Sync Frame ID Table Content
750
26.6.12.2 Sync Frame Deviation Table Content
750
26.6.12.3 Sync Frame ID and Sync Frame Deviation Table Setup
750
26.6.12.4 Sync Frame ID and Sync Frame Deviation Table Generation
751
26.6.12.5 Sync Frame Table Access
752
26.6.13 MTS Generation
752
26.6.14 Key Slot Transmission
753
26.6.14.1 Key Slot Assignment
753
26.6.14.2 Key Slot Transmission in POC:startup
753
26.6.14.3 Key Slot Transmission in POC:normal active
753
26.6.15 Sync Frame Filtering
753
26.6.15.1 Sync Frame Acceptance Filtering
754
26.6.15.2 Sync Frame Rejection Filtering
754
26.6.16 Strobe Signal Support
754
26.6.16.1 Strobe Signal Assignment
754
26.6.16.2 Strobe Signal Timing
755
26.6.17 Timer Support
755
26.6.17.1 Absolute Timer T1
756
26.6.17.2 Absolute / Relative Timer T2
756
26.6.18 Slot Status Monitoring
756
26.6.18.1 Channel Status Error Counter Registers
758
26.6.18.2 Protocol Status Registers
759
26.6.18.3 Slot Status Registers
759
26.6.18.4 Slot Status Counter Registers
759
26.6.18.5 Message Buffer Slot Status Field
760
26.6.19 System Bus Access
760
26.6.19.1 System Bus Illegal Address Access
761
26.6.19.2 System Bus Access Timeout
761
26.6.19.3 Continue after System Bus Failure
761
26.6.19.4 Freeze after System Bus Failure
762
26.6.20 Interrupt Support
762
26.6.20.1 Individual Interrupt Sources
762
26.6.20.2 Combined Interrupt Sources
763
26.6.21 Lower Bit Rate Support
765
26.7 Application Information
766
26.7.1 Initialization Sequence
766
26.7.1.1 Module Initialization
766
26.7.1.2 Protocol Initialization
767
26.7.2 Shut Down Sequence
767
26.7.3 Number of Usable Message Buffers
767
26.7.4 Protocol Control Command Execution
768
26.7.5 Message Buffer Search on Simple Message Buffer Configuration
769
26.7.5.1 Simple Message Buffer Configuration
769
26.7.5.2 Behavior in Static Segment
771
26.7.5.3 Behavior in Dynamic Segment
771
Chapter 27 Media Local Bus (MLB)
773
27.1 Introduction
773
27.1.1 Block Diagram
773
27.1.2 Features
774
27.1.3 Overview
774
27.1.4 Modes of Operation
775
27.2 External Signal Description
775
27.3 Memory Map and Register Description
776
27.3.1 Memory Map
776
27.3.2 Register Descriptions
780
27.3.2.1 Device Control Configuration Register (DCCR)
780
27.3.2.2 System Status Configuration Register (SSCR)
782
27.3.2.3 System Data Configuration Register (SDCR)
783
27.3.2.4 System Mask Configuration Register (SMCR)
784
27.3.2.5 Version Control Configuration Register (VCCR)
785
27.3.2.6 Synchronous Base Address Configuration Register (SBCR)
786
27.3.2.7 Asynchronous Base Address Configuration Register (ABCR)
786
27.3.2.8 Control Base Address Configuration Register (CBCR)
787
27.3.2.9 Isochronous Base Address Configuration Register (IBCR)
788
27.3.2.10 Channel Interrupt Configuration Register (CICR)
788
27.3.2.11 Channel n Entry Configuration Register
789
27.3.2.12 Channel n Status Configuration Register
791
27.3.2.13 Channel n Current Buffer Configuration Register
794
27.3.2.14 Channel n Next Buffer Configuration Register
795
27.3.2.15 Local Channel n Buffer Configuration Register
796
27.4 Functional Description
798
27.4.1 Clocking Requirements
800
27.4.1.1 Reset
800
27.4.2 Interrupts
800
27.4.3 System Memory Buffers
801
27.4.4 Local Channel Buffer RAM
802
27.4.4.1 Local Buffer Start Address
802
27.4.4.2 Local Channel Buffer Depth
802
27.4.5 Channel Arbiter
803
27.4.5.1 Round Robin Arbitration
803
27.4.6 DMA Controller (Ping-Pong Buffering)
804
27.4.6.1 Asynchronous and Control Packet Handling
804
27.4.6.2 Isochronous and Synchronous Data Handling
807
27.4.7 DMA Controller (Circular Buffering)
808
27.4.8 Streaming Channel Frame Synchronization
810
27.4.9 Loop Back Test Mode
811
27.5 Initialization Information
811
27.5.1 Main Loop
812
27.5.2 Initialize Device
813
27.5.3 Initialize Channel
814
27.5.4 Channel Interrupts
816
27.5.5 System Interrupts
820
Chapter 28 Enhanced Modular Input/Output Subsystem (eMIOS200)
823
28.1 Introduction
823
28.1.1 Block Diagram
823
28.1.2 Features
824
28.1.3 Modes of Operation
825
28.1.4 eMIOS200 Channel Configurations
825
28.1.4.1 Type A: Counter Channels
826
28.1.4.2 Type B: Complex Channels
827
28.1.4.3 Type C: Lighting Channels
827
28.2 External Signal Description
828
28.2.1 eMIOS[n]
828
28.2.2 Output Disable Input - eMIOS200 Output Disable Input Signal
828
28.3 Memory Map and Register Description
828
28.3.1 Memory Map
828
28.3.2 Register Descriptions
830
28.3.2.1 eMIOS200 Module Configuration Register (EMIOS_MCR)
831
28.3.2.2 eMIOS200 Global Flag Register (EMIOS_GFR)
832
28.3.2.3 eMIOS200 Output Update Disable Register (EMIOS_OUDR)
833
28.3.2.4 eMIOS200 Disable Channel Register (EMIOS_UCDIS)
833
28.3.2.5 eMIOS200 A Register (EMIOS_CADR[n])
834
28.3.2.6 eMIOS200 B Register (EMIOS_CBDR[n])
834
28.3.2.7 eMIOS200 Counter Register (EMIOS_CCNTR[n])
835
28.3.2.8 eMIOS200 Control Register (EMIOS_CCR[n])
836
28.3.2.9 eMIOS200 Status Register (EMIOS_CSR[n])
841
28.3.2.10 eMIOS200 Alternate A Register (EMIOS_ALTA[n])
842
28.4 Functional Description
842
28.4.1 Unified Channel (UC)
842
28.4.1.1 Unified Channel Modes of Operation
844
28.4.1.2 Input Programmable Filter (IPF)
879
28.4.1.3 Clock Prescaler (CP)
880
28.4.1.4 Effect of Freeze on the Unified Channel
880
28.4.2 IP Bus Interface Unit (BIU)
881
28.4.2.1 Effect of Freeze on the BIU
881
28.4.3 Global Clock Prescaler Submodule (GCP)
881
28.4.3.1 Effect of Freeze on the GCP
881
28.5 Reset
881
28.6 Interrupts
881
28.7 DMA Requests
881
28.8 Initialization/Application Information
882
28.8.1 Considerations
882
28.8.2 Application Information
882
28.8.3 Time Base Generation
882
28.8.4 Coherent Accesses
884
Chapter 29 Controller Area Network (FlexCAN)
885
29.1 Introduction
885
29.1.1 Block Diagram
885
29.1.2 Features
886
29.1.3 Modes of Operation
887
29.1.3.1 Normal Mode
887
29.1.3.2 Freeze Mode
887
29.1.3.3 Listen-Only Mode
888
29.1.3.4 Loop-Back Mode
888
29.1.3.5 Module-Disabled Mode
888
29.1.3.6 Halt Mode
888
29.2 External Signal Description
888
29.3 Memory Map and Registers
888
29.3.1 Module Memory Map
888
29.3.2 Message Buffer Structure
891
29.3.3 Rx FIFO Structure
893
29.3.4 Register Descriptions
895
29.3.4.1 Module Configuration Register (CANx_MCR)
895
29.3.4.2 Control Register (CANx_CTRL)
898
29.3.4.3 Free-Running Timer (CANx_TIMER)
901
29.3.4.4 Rx Mask Registers
901
29.3.4.5 Error Counter Register (CANx_ECR)
904
29.3.4.6 Error and Status Register (CANx_ESR)
905
29.3.4.7 Interrupt Masks 2 Register (CANx_IMASK2)
907
29.3.4.8 Interrupt Masks 1 Register (CANx_IMASK1)
908
29.3.4.9 Interrupt Flags 2 Register (CANx_IFLAG2)
908
29.3.4.10 Interrupt Flags 1 Register (CANx_IFLAG1)
909
29.3.4.11 Rx Individual Mask Registers (CANx_RXIMR0 - CANx_RXIMR63)
910
29.4 Functional Description
911
29.4.1 Transmit Process
912
29.4.2 Arbitration Process
912
29.4.3 Receive Process
913
29.4.4 Matching Process
914
29.4.5 Data Coherence
915
29.4.5.1 Transmission Abort Mechanism
916
29.4.5.2 Message Buffer Deactivation
916
29.4.5.3 Message Buffer Lock Mechanism
917
29.4.6 Rx FIFO
918
29.4.7 CAN Protocol Related Features
919
29.4.7.1 Remote Frames
919
29.4.7.2 Overload Frames
919
29.4.7.3 Time Stamp
919
29.4.7.4 Protocol Timing
920
29.4.7.5 Arbitration and Matching Timing
922
29.4.8 Modes of Operation Details
922
29.4.8.1 Freeze Mode
922
29.4.8.2 Module Disabled Mode
923
29.4.9 Interrupts
923
29.4.10 Bus Interface
924
29.5 Initialization and Application Information
924
29.5.1 FlexCAN Initialization Sequence
924
Chapter 30 Deserial - Serial Peripheral Interface (DSPI)
927
30.1 Introduction
927
30.1.1 Block Diagram
928
30.1.2 Features
928
30.1.3 DSPI Configurations
929
30.1.3.1 SPI Configuration
930
30.1.3.2 DSI Configuration
930
30.1.3.3 CSI Configuration
930
30.1.4 Modes of Operation
930
30.1.4.1 Master Mode
930
30.1.4.2 Slave Mode
930
30.1.4.3 Module Disable Mode
930
30.1.4.4 Halt Mode
931
30.1.4.5 Debug Mode
931
30.2 External Signal Description
931
30.3 Memory Map and Registers
931
30.3.1 Module Memory Map
931
30.3.2 Register Descriptions
933
30.3.2.1 DSPI Module Configuration Register (DSPI_MCR)
933
30.3.2.2 DSPI Transfer Count Register (DSPI_TCR)
935
30.3.2.3 DSPI Clock and Transfer Attributes Registers 0-7 (DSPI_CTARn)
936
30.3.2.4 DSPI Status Register (DSPI_SR)
942
30.3.2.5 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)
944
30.3.2.6 DSPI PUSH TX FIFO Register (DSPI_PUSHR)
945
30.3.2.7 DSPI POP RX FIFO Register (DSPI_POPR)
947
30.3.2.8 DSPI Transmit FIFO Registers 0-15 (DSPI_TXFRn)
947
30.3.2.9 DSPI Receive FIFO Registers 0-3 (DSPI_RXFRn)
948
30.3.2.10 DSPI DSI Configuration Register (DSPI_DSICR)
949
30.3.2.11 DSPI DSI Serialization Data Register (DSPI_SDR)
950
30.3.2.12 DSPI DSI Alternate Serialization Data Register (DSPI_ASDR)
951
30.3.2.13 DSPI DSI Transmit Comparison Register (DSPI_COMPR)
952
30.3.2.14 DSPI DSI Deserialization Data Register (DSPI_DDR)
952
30.3.2.15 DSPI DSI Configuration Register 1 (DSPI_DSICR1)
953
30.4 Functional Description
954
30.4.1 Modes of Operation
955
30.4.1.1 Master Mode
955
30.4.1.2 Slave Mode
956
30.4.1.3 Module Disable Mode
956
30.4.1.4 Halt Mode
956
30.4.1.5 Debug Mode
957
30.4.2 Start and Stop of DSPI Transfers
957
30.4.3 Serial Peripheral Interface (SPI) Configuration
958
30.4.3.1 SPI Master Mode
958
30.4.3.2 SPI Slave Mode
958
30.4.3.3 FIFO Disable Operation
959
30.4.3.4 Transmit First-In First-Out (TX FIFO) Buffering Mechanism
959
30.4.3.5 Receive First-In First-Out (RX FIFO) Buffering Mechanism
960
30.4.4 Deserial Serial Interface (DSI) Configuration
961
30.4.4.1 DSI Master Mode
961
30.4.4.2 DSI Slave Mode
961
30.4.4.3 DSI Serialization
961
30.4.4.4 DSI Deserialization
962
30.4.4.5 DSI Transfer Initiation Control
963
30.4.5 Combined Serial Interface (CSI) Configuration
963
30.4.5.1 CSI Serialization
964
30.4.5.2 CSI Deserialization
965
30.4.6 Buffered SPI Operation
966
30.4.7 DSPI Baud Rate and Clock Delay Generation
966
30.4.7.1 Baud Rate Generator
966
30.4.7.2 PCS to SCK Delay (tCSC)
967
30.4.7.3 After SCK Delay (tASC)
967
30.4.7.4 Delay after Transfer (tDT)
968
30.4.7.5 Peripheral Chip Select Strobe Enable (PCSS)
969
30.4.8 Transfer Formats
970
30.4.8.1 Classic SPI Transfer Format (CPHA = 0)
971
30.4.8.2 Classic SPI Transfer Format (CPHA = 1)
972
30.4.8.3 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 0)
973
30.4.8.4 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1)
974
30.4.8.5 Continuous Selection Format
975
30.4.8.6 Clock Polarity Switching Between DSPI Transfers
977
30.4.9 Continuous Serial Communications Clock
977
30.4.10 Timed Serial Bus (TSB)
979
30.4.10.1 PCS Switch Over Timing
980
30.4.10.2 TSB Command Frame Format
981
30.4.10.3 TSB Data Frame Format
981
30.4.11 Peripheral Chip Select Expansion and Deglitching
982
30.4.12 DMA and Interrupt Conditions
982
30.4.12.1 End of Queue Interrupt Request (EOQF)
983
30.4.12.2 Transmit FIFO Fill Interrupt or DMA Request (TFFF)
983
30.4.12.3 Transfer Complete Interrupt Request (TCF)
983
30.4.12.4 Transmit FIFO Underflow Interrupt Request (TFUF)
983
30.4.12.5 Receive FIFO Drain Interrupt or DMA Request (RFDF)
983
30.4.12.6 Receive FIFO Overflow Interrupt Request
984
30.4.12.7 DMA Requests
984
30.4.12.8 Interrupt Requests
984
30.4.13 Power Saving Features
984
30.4.13.1 Halt Mode
984
30.4.13.2 Module Disable Mode
984
30.4.13.3 Slave Interface Signal Gating
985
30.5 Initialization/Application Information
985
30.5.1 How to Change Queues
985
30.5.2 Baud Rate Settings
986
30.5.3 Delay Settings
986
30.5.4 Oak Family Compatibility with the DSPI
987
30.5.5 Calculation of FIFO Pointer Addresses
988
30.5.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO
989
30.5.5.2 Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO
989
Chapter 31 Enhanced Serial Communication Interface (eSCI)
991
31.1 Introduction
991
31.1.1 Block Diagram
991
31.1.2 Features
991
31.1.3 Modes of Operation
993
31.1.3.1 SCI Mode
993
31.1.3.2 LIN Mode
993
31.1.3.3 Disabled Mode
993
31.1.3.4 Halt Mode
993
31.2 External Signal Description
994
31.3 Memory Map and Registers
994
31.3.1 Memory Map
994
31.3.2 Register Descriptions
995
31.3.2.1 eSCI Baud Rate Register (eSCI_BRR)
996
31.3.2.2 eSCI Control Register 1 (eSCI_CR1)
996
31.3.2.3 eSCI Control Register 2 (eSCI_CR2)
998
31.3.2.4 eSCI Data Register (eSCI_DR)
1000
31.3.2.5 eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1)
1001
31.3.2.6 eSCI Interrupt Flag and Status Register 2 (eSCI_IFSR2)
1002
31.3.2.7 eSCI LIN Control Register 1 (eSCI_LCR1)
1003
31.3.2.8 eSCI LIN Control Register 2 (eSCI_LCR2)
1005
31.3.2.9 eSCI LIN Transmit Register (eSCI_LTR)
1005
31.3.2.10 eSCI LIN Receive Register (eSCI_LRR)
1007
31.3.2.11 eSCI LIN CRC Polynomial Register (eSCI_LPR)
1008
31.3.2.12 eSCI Control Register 3 (eSCI_CR3)
1008
31.4 Functional Description
1010
31.4.1 Module Control
1010
31.4.2 Frame Formats
1010
31.4.2.1 Data Frame Formats
1010
31.4.2.2 Break Character Formats
1012
31.4.2.3 Idle Character Formats
1013
31.4.3 Baud Rate and Clock Generation
1013
31.4.3.1 Module Clock
1014
31.4.3.2 Transmitter Clock
1014
31.4.3.3 Receiver Clock
1014
31.4.4 Baud Rate Tolerance
1015
31.4.4.1 Faster Receiver Tolerance
1015
31.4.4.2 Slower Receiver Tolerance
1016
31.4.5 SCI Mode
1017
31.4.5.1 SCI Mode Configuration
1017
31.4.5.2 Transmitter
1017
31.4.5.3 Receiver
1022
31.4.5.4 Reception Error Reporting
1031
31.4.5.5 Multiprocessor Communication
1031
31.4.6 LIN Mode
1032
31.4.6.1 LIN Mode Configuration
1032
31.4.6.2 LIN Frame Formats
1033
31.4.6.3 LIN TX Frame Generation
1034
31.4.6.4 LIN RX Frame Generation
1036
31.4.6.5 LIN Error Reporting
1038
31.4.6.6 LIN Wakeup
1040
31.4.6.7 LIN Protocol Engine Reset
1041
31.4.7 Interrupts
1041
31.4.7.1 Interrupt Flags and Enables
1041
31.4.7.2 Interrupt Request Generation
1042
31.5 Application Information
1042
31.5.1 SCI Data Frames Separated by Preamble
1042
Chapter 32 Inter-Integrated Circuit Bus Controller Module (I2C)
1045
32.1 Introduction
1045
32.1.1 Block Diagram
1045
32.1.2 DMA Interface
1046
32.1.3 Features
1047
32.1.4 Modes of Operation
1048
32.2 External Signal Description
1048
32.3 Memory Map and Registers
1048
32.3.1 Module Memory Map
1048
32.3.2 Register Descriptions
1049
32.3.2.1 I2C Bus Address Register (IBAD)
1049
32.3.2.2 I2C Bus Frequency Divider Register (IBFD)
1049
32.3.2.3 I2C Bus Control Register (IBCR)
1052
32.3.2.4 I2C Bus Status Register (IBSR)
1053
32.3.2.5 I2C Bus Data I/O Register (IBDR)
1054
32.3.2.6 I2C Bus Interrupt Configuration Register (IBIC)
1055
32.4 Functional Description
1055
32.4.1 I-Bus Protocol
1055
32.4.1.1 START Signal
1056
32.4.1.2 Slave Address Transmission
1057
32.4.1.3 Data Transfer
1057
32.4.1.4 STOP Signal
1057
32.4.1.5 Repeated START Signal
1058
32.4.1.6 Arbitration Procedure
1058
32.4.1.7 Clock Synchronization
1058
32.4.1.8 Handshaking
1059
32.4.1.9 Clock Stretching
1059
32.4.2 Interrupts
1059
32.4.2.1 General
1059
32.4.2.2 Interrupt Description
1059
32.5 Initialization/Application Information
1060
32.5.1 I2C Programming Examples
1060
32.5.1.1 Initialization Sequence
1060
32.5.1.2 Generation of START
1060
32.5.1.3 Post-Transfer Software Response
1060
32.5.1.4 Generation of STOP
1061
32.5.1.5 Generation of Repeated START
1062
32.5.1.6 Slave Mode
1062
32.5.1.7 Arbitration Lost
1062
32.5.2 DMA Application Information
1064
32.5.2.1 DMA Mode, Master Transmit
1064
32.5.2.2 DMA Mode, Master RX
1065
32.5.2.3 Exiting DMA Mode, System Requirement Considerations
1066
Chapter 33 Cross Triggering Unit (CTU)
1069
33.1 Introduction
1069
33.2 Main Features
1069
33.3 Block Diagram
1069
33.4 Memory Map and Register Description
1070
33.4.1 Module Memory Map
1070
33.4.1.1 Control Status Register (CTU_CSR)
1072
33.4.1.2 Start Value Register (CTU_SVRn)
1073
33.4.1.3 Current Value Register (CTU_CVRm)
1073
33.4.1.4 Event Configuration Register (CTU_EVTCFGRn)
1074
33.5 Functional Description
1075
33.5.1 Pending Request
1078
33.5.2 Counter
1078
33.5.3 Prescaler
1078
33.5.4 Trigger Interrupt Request
1079
33.5.5 Halt Request
1079
33.5.6 Channel Value
1079
Chapter 34 Analog-to-Digital Converter (ADC)
1081
34.1 Introduction
1081
34.1.1 Block Diagram
1081
34.1.2 Features
1082
34.2 External Signals
1082
34.3 Memory Map and Register Definition
1083
34.3.1 ADC Memory Map
1083
34.3.2 ADC Register Descriptions
1088
34.3.2.1 Main Configuration Register (MCR)
1088
34.3.2.2 Main Status Register (MSR)
1090
34.3.2.3 Interrupt Status Register (ISR)
1091
34.3.2.4 Channel Pending Register 0 (CEOCFR0)
1092
34.3.2.5 Channel Pending Register 1 (CEOCFR1)
1093
34.3.2.6 Channel Pending Register 2 (CEOCFR2)
1093
34.3.2.7 Interrupt Mask Register (IMR)
1094
34.3.2.8 Channel Interrupt Mask Register 0 (CIMR0)
1095
34.3.2.9 Channel Interrupt Mask Register 1 (CIMR1)
1095
34.3.2.10 Channel Interrupt Mask Register 2 (CIMR2)
1096
34.3.2.11 Watchdog Threshold Interrupt Status Register (WTISR)
1096
34.3.2.12 Watchdog Threshold Interrupt Mask Register (WTIMR)
1097
34.3.2.13 DMA Enable Register (DMAE)
1098
34.3.2.14 DMA Channel Select Register 0 (DMAR0)
1098
34.3.2.15 DMA Channel Select Register 1 (DMAR1)
1099
34.3.2.16 DMA Channel Select Register 2 (DMAR2)
1099
34.3.2.17 Threshold Control Registers 0 - 3 (TRCn)
1100
34.3.2.18 Threshold Registers 0 - 3 (THRHLRn)
1101
34.3.2.19 Presampling Control Register (PSCR)
1102
34.3.2.20 Presampling Register 0 (PSR0)
1102
34.3.2.21 Presampling Register 1 (PSR1)
1103
34.3.2.22 Presampling Register 2 (PSR2)
1103
34.3.2.23 Conversion Timing Register 0 (CTR0)
1104
34.3.2.24 Conversion Timing Register 1 (CTR1)
1104
34.3.2.25 Conversion Timing Register 2 (CTR2)
1105
34.3.2.26 Normal Conversion Mask Register 0 (NCMR0)
1113
34.3.2.27 Normal Conversion Mask Register 1 (NCMR1)
1114
34.3.2.28 Normal Conversion Mask Register 2 (NCMR2)
1114
34.3.2.29 Injected Conversion Mask Register 0 (JCMR0)
1115
34.3.2.30 Injected Conversion Mask Register 1 (JCMR1)
1115
34.3.2.31 Injected Conversion Mask Register 2 (JCMR2)
1116
34.3.2.32 Offset Word Register (OFFWR)
1116
34.3.2.33 Decode Signals Delay Register (DSDR)
1117
34.3.2.34 Power Down Exit Delay Register (PDEDR)
1118
34.3.2.35 Precision Channel n Data Register (PRECDATAREGn)
1118
34.3.2.36 Internal Channel n Data Register (INTDATAREGn)
1119
34.3.2.37 External Channel n Data Register (EXTDATAREGn)
1119
34.4 Functional Description
1121
34.4.1 Analog Channel Conversion
1121
34.4.1.1 Normal Conversion
1121
34.4.1.2 Start of Normal Conversion
1121
34.4.1.3 Normal Conversion Operating Modes
1122
34.4.1.4 Injected Channel Conversion
1123
34.4.1.5 Abort Conversion
1124
34.4.2 Analog Clock Generator and Conversion Timings
1124
34.4.3 ADC Cross Triggering Unit
1125
34.4.3.1 CTU Trigger Mode
1126
34.4.3.2 CTU Control Mode
1126
34.4.4 Presampling
1128
34.4.4.1 Presampling Channel Enable Signals
1129
34.4.5 Programmable Analog Watchdog
1129
34.4.5.1 Analog Watchdog Pulse Width Modulation Bus
1131
34.4.6 DMA Functionality
1131
34.4.7 Interrupts
1132
34.4.8 External Decode Signals Delay
1133
34.4.9 Power Down Mode
1133
34.4.10 Auto Clock Off Mode
1133
Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC)
1135
35.1 Introduction
1135
35.1.1 Block Diagram
1135
35.1.1.1 Individual and Multi-Core Debug
1136
35.1.2 Features
1137
35.1.3 Modes of Operation
1137
35.1.3.1 Reset
1138
35.1.3.2 IEEE 1149.1-2001 Defined Test Modes
1138
35.1.3.3 Bypass Mode
1138
35.1.3.4 TAP Sharing Mode
1138
35.2 External Signal Description
1139
35.3 Memory Map and Registers
1139
35.3.1 Instruction Register
1139
35.3.2 Bypass Register
1139
35.3.3 Device Identification Register
1140
35.3.4 Boundary Scan Register
1140
35.4 Functional Description
1140
35.4.1 JTAGC Reset Configuration
1140
35.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port
1141
35.4.3 TAP Controller State Machine
1141
35.4.3.1 Enabling the TAP Controller
1143
35.4.3.2 Selecting an IEEE 1149.1-2001 Register
1143
35.4.4 JTAGC Instructions
1143
35.4.4.1 BYPASS Instruction
1144
35.4.4.2 ACCESS_AUX_TAP_x Instructions
1144
35.4.4.3 CLAMP Instruction
1144
35.4.4.4 EXTEST-External Test Instruction
1145
35.4.4.5 HIGHZ Instruction
1145
35.4.4.6 IDCODE Instruction
1145
35.4.4.7 SAMPLE Instruction
1145
35.4.4.8 SAMPLE/PRELOAD Instruction
1145
35.4.5 Boundary Scan
1146
35.5 e200z0 and e200z6 OnCE Controllers
1146
35.5.1 e200z0 OnCE Controller Block Diagram
1146
35.5.2 e200z0 OnCE Controller Functional Description
1147
35.5.2.1 Enabling the TAP Controller
1147
35.5.3 e200z0 OnCE Controller Register Descriptions
1147
35.5.3.1 OnCE Command Register (OCMD)
1147
35.6 Initialization/Application Information
1149
Chapter 36 Nexus Development Interface (NDI)
1151
36.1 Introduction
1151
36.2 Block Diagram
1151
36.2.1 NDI Features
1153
36.2.2 Modes of Operation
1155
36.2.2.1 Nexus Reset Mode
1155
36.2.2.2 Full-Port Mode
1156
36.2.2.3 Reduced-Port Mode
1156
36.2.2.4 Disabled-Port Mode
1156
36.2.2.5 Censored Mode
1156
36.2.2.6 Halt Mode
1156
36.3 External Signal Description
1156
36.4 Memory Map and Registers
1157
36.4.1 NDI Functional Description
1159
36.4.1.1 Enabling Nexus Clients for TAP Access
1159
36.4.1.2 TAP Sharing
1159
36.4.1.3 Configuring the NDI for Nexus Messaging
1159
36.4.1.4 Programmable MCKO Frequency
1160
36.4.1.5 Nexus Messaging
1160
36.4.1.6 e200z6 and e200z0 Cross Triggering Control
1161
36.5 Nexus Port Controller (NPC)
1163
36.5.1 NPC Overview
1163
36.5.2 NPC Features
1164
36.5.3 Control of the device-wide debug mode NPC Memory Map
1164
36.5.4 NPC Register Descriptions
1164
36.5.4.1 Bypass Register
1164
36.5.4.2 Instruction Register
1164
36.5.4.3 Nexus Device ID Register (DID)
1165
36.5.4.4 Port Configuration Register (PCR)
1166
36.5.5 NPC Functional Description
1168
36.5.5.1 NPC Reset Configuration
1168
36.5.5.2 Auxiliary Output Port
1168
36.5.6 NPC Initialization/Application Information
1173
36.6 e200z6 Class 3 Nexus Module (Nexus3+)
1174
36.6.1 Nexus3+ Introduction
1174
36.6.2 Nexus3+ Block Diagram
1175
36.6.3 Nexus3+ Overview
1175
36.6.4 Nexus3+ Features
1176
36.6.5 Enabling Nexus3+ Operation
1177
36.6.6 TCODEs Supported by Nexus3+
1177
36.6.7 Nexus3+ Memory Map
1181
36.6.8 Nexus3+ Register Definition
1182
36.6.8.1 Development Control Register 1, 2 (DC1, DC2)
1182
36.6.8.2 Development Status Register (DS)
1184
36.6.8.3 Read/Write Access Control/Status (RWCS)
1185
36.6.8.4 Read/Write Access Address (RWA)
1186
36.6.8.5 Read/Write Access Data (RWD)
1186
36.6.8.6 Watchpoint Trigger Register (WT)
1188
36.6.8.7 Data Trace Control Register (DTC)
1190
36.6.8.8 Data Trace Start Address Registers 1 and 2 (DTSAn)
1191
36.6.8.9 Data Trace End Address Registers 1 and 2 (DTEAn)
1191
36.6.9 Nexus3+ Register Access via JTAG / OnCE
1192
36.6.10 Nexus3+ Functional Description
1193
36.6.10.1 Debug Status Messages
1193
36.6.10.2 Ownership Trace
1193
36.6.10.3 Program Trace
1195
36.6.10.4 Data Trace
1205
36.6.10.5 Watchpoint Support
1210
36.6.10.6 Nexus3+ Read/Write Access to Memory-Mapped Resources
1212
36.6.10.7 Examples
1217
36.6.10.8 IEEE 1149.1 (JTAG) RD/WR Sequences
1218
36.7 e200z0 Class 2+ Nexus Module (Nexus2+)
1220
36.7.1 Nexus2+ Introduction
1220
36.7.2 Nexus2+ Block Diagram
1221
36.7.3 Nexus2+ Features
1221
36.7.4 Enabling Nexus2+ Operation
1222
36.7.5 TCODEs Supported by Nexus2+
1222
36.7.6 Nexus2+ Memory Map
1225
36.7.7 Nexus2+ Register Definition
1226
36.7.7.1 Development Control Register 1, 2 (DC1, DC2)
1226
36.7.7.2 Development Status Register (DS)
1228
36.7.7.3 Read/Write Access Control/Status (RWCS)
1228
36.7.7.4 Read/Write Access Address (RWA)
1230
36.7.7.5 Read/Write Access Data (RWD)
1230
36.7.7.6 Watchpoint Trigger Register (WT)
1231
36.7.8 Nexus2+ Register Access via JTAG / OnCE
1232
36.7.9 Nexus2+ Functional Description
1233
36.7.9.1 Debug Status Messages
1233
36.7.9.2 Ownership Trace
1233
36.7.9.3 Program Trace
1235
36.7.9.4 Watchpoint Support
1244
36.7.9.5 Nexus2+ Read/Write Access to Memory-Mapped Resources
1246
36.7.9.6 Examples
1250
36.7.9.7 IEEE 1149.1 (JTAG) RD/WR Sequences
1251
36.8 Debug Implementation
1252
36.9 Debug Capabilities
1252
36.10 Debug Port
1254
36.10.1 Nexus2+/3 Auxiliary Port
1255
36.11 Debug Methods
1256
36.11.1 208 MAPBGA Package Debug Method
1256
36.11.2 256 MAPBGA Package Debug Method
1256
Appendix A Memory Map
1259
Related product manuals
NXP Semiconductors UM10204
64 pages
NXP Semiconductors K22F series
1407 pages
NXP Semiconductors LPC1311
368 pages
To Next Page
